Altera DE2-70 User Manual page 56

Figure 5.18. TV Decoder schematic.
Signal Name FPGA Pin No.
TD1_D[0] PIN_A6
TD1_D[1] PIN_B6
TD1_D[2] PIN_A5
TD1_D[3] PIN_B5
TD1_D[4] PIN_B4
TD1_D[5] PIN_C4
TD1_D[6] PIN_A3
TD1_D[7] PIN_B3
TD1_HS PIN_E13
TD1_VS PIN_E14
Description
TV Decoder 1 Data[0]
TV Decoder 1 Data[1]
TV Decoder 1 Data[2]
TV Decoder 1 Data[3]
TV Decoder 1 Data[4]
TV Decoder 1 Data[5]
TV Decoder 1 Data[6]
TV Decoder 1 Data[7]
TV Decoder 1 H_SYNC
TV Decoder 1 V_SYNC
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DE2-70 User Manual