Table of Contents
Advertisement
found on the manufacturer's web site, or in the Datasheet/VGA DAC folder on the DE2-70 System
CD-ROM. The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table
5.11. An example of code that drives a VGA display is described in Sections 6.2, 6.3 and 6.4.
Configuration
VGA(60Hz)
VGA(85Hz)
SVGA(60Hz)
SVGA(75Hz)
SVGA(85Hz)
XGA(60Hz)
XGA(70Hz)
XGA(85Hz)
1280x1024(60Hz)
Configuration
VGA(60Hz)
VGA(85Hz)
SVGA(60Hz)
SVGA(75Hz)
SVGA(85Hz)
XGA(60Hz)
XGA(70Hz)
XGA(85Hz)
1280x1024(60Hz)
Figure 5.13. VGA horizontal timing specification.
VGA mode
Resolution(HxV)
a(us)
640x480
640x480
800x600
800x600
800x600
1024x768
1024x768
1024x768
1280x1024
Table 5.9. VGA horizontal timing specification.
VGA mode
Resolution (HxV)
640x480
640x480
800x600
800x600
800x600
1024x768
1024x768
1024x768
1280x1024
Table 5.10. VGA vertical timing specification.
Horizontal Timing Spec
b(us)
c(us)
d(us)
3.8
1.9
25.4
0.6
1.6
2.2
17.8
1.6
3.2
2.2
20
1
1.6
3.2
16.2
0.3
1.1
2.7
14.2
0.6
2.1
2.5
15.8
0.4
1.8
1.9
13.7
0.3
1.0
2.2
10.8
0.5
1.0
2.3
11.9
0.4
Vertical Timing Spec
a(lines)
b(lines)
2
33
3
25
4
23
3
21
3
27
6
29
6
29
3
36
3
38
46
DE2-70 User Manual
Pixel clock(Mhz)
25
(640/c)
36
(640/c)
40
(800/c)
49
(800/c)
56
(800/c)
65
(1024/c)
75
(1024/c)
95
(1024/c)
108 (1280/c)
c(lines)
d(lines)
480
10
480
1
600
1
600
1
600
1
768
3
768
3
768
1
1024
1
Hide quick links:
Advertisement
Table of Contents
