Altera DE2-70 User Manual page 54

Figure 5.17. Fast Ethernet schematic.
Signal Name FPGA Pin No.
ENET_DATA[0] PIN_A23
ENET_DATA[1] PIN_C22
ENET_DATA[2] PIN_B22
ENET_DATA[3] PIN_A22
ENET_DATA[4] PIN_B21
ENET_DATA[5] PIN_A21
ENET_DATA[6] PIN_B20
ENET_DATA[7] PIN_A20
ENET_DATA[8] PIN_B26
ENET_DATA[9] PIN_A26
ENET_DATA[10] PIN_B25
ENET_DATA[11] PIN_A25
ENET_DATA[12] PIN_C24
ENET_DATA[13] PIN_B24
ENET_DATA[14] PIN_A24
ENET_DATA[15] PIN_B23
ENET_CLK PIN_D27
ENET_CMD PIN_B27
Description
DM9000A DATA[0]
DM9000A DATA[1]
DM9000A DATA[2]
DM9000A DATA[3]
DM9000A DATA[4]
DM9000A DATA[5]
DM9000A DATA[6]
DM9000A DATA[7]
DM9000A DATA[8]
DM9000A DATA[9]
DM9000A DATA[10]
DM9000A DATA[11]
DM9000A DATA[12]
DM9000A DATA[13]
DM9000A DATA[14]
DM9000A DATA[15]
DM9000A Clock 25 MHz
DM9000A Command/Data Select, 0 = Command, 1 = Data
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DE2-70 User Manual