Altera DE2-70 User Manual page 42

SMA
Connector
50-MHz
Oscillator
28-MHz TV
Oscillator decoder 1
TV
decoder 2
Figure 5.8. Block diagram of the clock distribution.
Signal Name
CLK_28
CLK_50
CLK_50_2
CLK_50_3
CLK_50_4
EXT_CLOCK
Table 5.5. Pin assignments for the clock inputs.
GPIO_0
2
4
SDRAM SDRAM
1 2
FPGA Pin No.
PIN_E16
PIN_AD15
PIN_D16
PIN_R28
PIN_R3
PIN_R29
39
GPIO_1
2
2
2
Cyclone II
FPGA
SSRAM
Description
28 MHz clock input
50 MHz clock input
50 MHz clock input
50 MHz clock input
50 MHz clock input
External (SMA) clock input
DE2-70 User Manual
SD Card
AUDIO
CODEC
4
PS/2
2
Ethernet
VGA
DAC
FLASH