Implementing A Tv Encoder - Altera DE2-70 User Manual

TD1_CLK27
TD1_RESET_N
TD2_D[0]
TD2_D[1]
TD2_D[2]
TD2_D[3]
TD2_D[4]
TD2_D[5]
TD2_D[6]
TD2_D[7]
TD2_HS
TD2_VS
TD2_CLK27
TD2_RESET_N
I2C_SCLK
I2C_SDAT

5.13 Implementing a TV Encoder

Although the DE2-70 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed
triple ADCs) can be used to implement a professional-quality TV encoder with the digital
processing part implemented in the Cyclone II FPGA. Figure 5.19 shows a block diagram of a TV
encoder implemented in this manner.
Clock
Timing
V
Figure 5.19. A TV Encoder that uses the Cyclone II FPGA and the ADV7123.
PIN_G15
PIN_D14
PIN_C10
PIN_A9
PIN_B9
PIN_C9
PIN_A8
PIN_B8
PIN_A7
PIN_B7
PIN_E15
PIN_D15
PIN_H15
PIN_B10
PIN_J18
PIN_H18
Table 5.16. TV Decoder pin assignments.
TV Encoder Block
(Cyclone II 2C70)
DSP Block
(Calculate
Sync
Composite)
Gen
DSP Block
Y
S-Video
SIN
(Y/C)
U
COS
Tables
TV Decoder 1 Clock Input.
TV Decoder 1 Reset
TV Decoder 2 Data[0]
TV Decoder 2 Data[1]
TV Decoder 2 Data[2]
TV Decoder 2 Data[3]
TV Decoder 2 Data[4]
TV Decoder 2 Data[5]
TV Decoder 2 Data[6]
TV Decoder 2 Data[7]
TV Decoder 2 H_SYNC
TV Decoder 2 V_SYNC
TV Decoder 2 Clock Input.
TV Decoder 2 Reset
I2C Data
I2C Clock
10-bit VGA DAC
O (Composite)
= Y + U.cos + V.sin
DAC
or Y (S-Video)
10-bit
or RCA_Y
C = U.cos + V.sin
(S-Video)
DAC
or RCA_Pb
10-bit
RCA_Pr
DAC
10-bit
54
DE2-70 User Manual