Figure 28: Reference Circuit Of Sgmii Interface With Phy Ar8033 Application - Quectel EC21 Series Hardware Design

Module
Control
SGMII_MDATA
SGMII Data

Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application

In order to enhance the reliability and availability in your application, please follow the criteria below in the
Ethernet PHY circuit design:

Keep SGMII data and control signals away from RF and VBAT trace.

Keep the maximum trace length less than 10inch and keep skew on the differential pairs less than
20mil.

The differential impedance of SGMII data trace is 100ohm±10%.

To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must
be equal to or larger than 40mil.
NOTE
For more information about SGMII application, please refer to document [5] and document [7].
EC21_Hardware_Design
EPHY_INT_N
EPHY_RST_N
SGMII_MCLK
USIM2_VDD
USIM2_VDD
C1 0.1uF
SGMII_RX_P
C2 0.1uF
SGMII_RX_M
SGMII_TX_P
SGMII_TX_M
R1 10K
VDD_EXT
R2
1.5K
USIM2_VDD
Close to Module
0.1uF
0.1uF
Close to AR8033
Confidential / Released
LTE Module Series
EC21 Hardware Design
AR8033
INT
RSTN
MDIO
MDC
SOP
SON
C3
SIP
C4
SIN
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