Table 13: Logic Levels Of Digital I/O - Quectel EC21 Series Hardware Design

The logic levels are described in the following table.

Table 13: Logic Levels of Digital I/O

Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8V UART interface. A level translator should be used if your application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instrument is
recommended. The following figure shows a reference design.
VDD_EXT
RI
DCD
CTS
RTS
DTR
TXD
RXD
Please visit http://www.ti.com for more information.
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module input and output circuit
designs; but please pay attention to the direction of connection.
EC21_Hardware_Design
Min.
-0.3
1.2
0
1.35
VCCA
0.1uF
OE
A1
A2
Translator
A3
A4
A5
A6
A7
51K
A8
Figure 20: Reference Circuit with Translator Chip
Confidential / Released
EC21 Hardware Design
Max.
0.6
2.0
0.45
1.8
VCCB
0.1uF
GND
B1
B2
B3
B4
B5
B6
B7
51K
B8
LTE Module Series
Unit
V
V
V
V
VDD_MCU
RI_MCU
DCD_MCU
CTS_MCU
RTS_MCU
DTR_MCU
TXD_MCU
RXD_MCU
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