Figure 24: Reference Circuit Of Pcm Application With Audio Codec - Quectel EC21 Series Hardware Design

PCM_CLK 27
I2C_SCL 41
I2C_SDA 42
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2] about AT+QDAI command for details.
The following figure shows a reference design of PCM interface with external codec IC.
PCM_CLK
PCM_SYNC
PCM_OUT
Module

Figure 24: Reference Circuit of PCM Application with Audio Codec

NOTES
"*" means under development.
1.
2. It is recommended to reserve RC (R=22 ohm, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
3. EC21 works as a master device pertaining to I2C interface.
EC21_Hardware_Design
IO PCM data bit clock
OD I2C serial clock
OD I2C serial data
PCM_IN
I2C_SCL
I2C_SDA
1.8V
MICBIAS
BCLK
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
Confidential / Released
LTE Module Series
EC21 Hardware Design
1.8V power domain
Require external pull-up to 1.8V
Require external pull-up to 1.8V
INP
INN
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