Figure 24: Reference Circuit Of Pcm Application With Audio Codec - Quectel EC25-V User Manual

PCM_OUT 25
PCM_SYNC 26
PCM_CLK 27
I2C_SCL 41
I2C_SDA 42
Clock and mode can be configured by AT command, and the default configuration is master mode using
short sync data format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Refer to document [2] about the
command AT+QDAI for details.
The following figure shows the reference design of PCM interface with external codec IC.
PCM_CLK
PCM_SYNC
PCM_OUT
I2C_SCL
I2C_SDA
Module

Figure 24: Reference Circuit of PCM Application with Audio Codec

NOTES
1. It is recommended to reserve RC (R=22ohm, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. EC25 works as a master device pertaining to I2C interface.
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DO PCM data output
IO PCM data frame sync signal
IO PCM data bit clock
OD I2C serial clock
OD I2C serial data
PCM_IN
1.8V
Confidential / Released
1.8V power domain
1.8V power domain
1.8V power domain
Require external pull-up to 1.8V
Require external pull-up to 1.8V
MICBIAS
INP
BCLK
INN
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
LTE Module Series
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