Wlan Interface; Bt Interface - Quectel EC21 Series Hardware Design

NOTES
1. FC20 module can only be used as a slave device,
2. When BT function is enabled on EC21 module, PCM_SYNC and PCM_CLK pins are only used to
output signals.
3. For more information about wireless connectivity interfaces, please refer to document [5].

3.18.1. WLAN Interface

EC21 provides a low power SDIO 3.0 interface and control interface for WLAN design.
SDIO interface supports the following modes:

Single data rate (SDR) mode (up to 200MHz)

Double data rate (DDR) mode (up to 52MHz)
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:

It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50 ohm (± 10%).

Protect other sensitive signals/circuits (RF, analog signals, etc.) from SDIO corruption and protect
SDIO signals from noisy signals (clocks, DCDCs, etc.).

It is recommended to keep matching length between CLK and DATA/CMD less than 1mm and total
routing length less than 50mm.

Keep termination resistors within 15~24 ohm on clock lines near the module and keep the route
distance from the module clock pins to termination resistors less than 5mm.

Make sure the adjacent trace spacing is 2x line width and bus capacitance is less than 15pF.

3.18.2. BT Interface*

EC21 supports a dedicated UART interface and a PCM interface for BT function application.
Further information about BT interface will be added in future version of this document.
NOTE
"*" means under development.
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