Pcb Design Rules; Layer Information; Layer Pcb - Texas Instruments CC3100 SimpleLink Wi-Fi User Manual

PCB Specification
3.2

PCB Design Rules

Parameter
Number of layers
Thickness
Size of PCB
Solder mask
Dielectric
Silk
Surface finish
Min track width
Min spacing
Mid drill diameter
Copper thickness
Lead free / ROHS
Impedance control
Impedance variation
3.3

Layer Information

The 4-layer PCB is used with the configuration, as shown in
Layer Usage
1 Signal + RF
2 GND
3 Power + signal
4 Power + signal
6
CC3100 and CC3200 SimpleLink™ Wi-Fi
Layout Guidelines
Table 1. PCB Design Rules
Value Comments
4
1.1 mm ± For greater thickness increase the distance between L2 and L3
10%
2.0" x 1.7"
Red Can be replaced with any color
FR4
White Can be replaced with any color
ENIG
6 mils Min track width can be reduced but cost would be higher
6 mils Min spacing can be reduced but the cost would be higher
8 mils 12-mil diameter drill is used on the Rev 3.3-A board
1 oz
Yes
Yes 50-Ω controlled impedance trace of 18-mils width on L1 w.r.t L2 (GND).
Air gap = 15 mils
Note: The above calculations are based on CPW-G (NOT microstrip).
5%
Table 2. 4 Layer PCB
Notes
RF trace is a CPW on L1 w.r.t. L2 ground
Reference plane for RF
The power planes for the power amplifier (PA), analog blocks and the main input supply are routed on
this layer
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Table 2.
SWRU370B – June 2014 – Revised August 2018
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