Response Delay Time - Mitsubishi Electric MELSEC iQ-R Series User Manual

Response delay time

This section describes the response delay time of the I/O signals and buffer memory areas of the pulse input module.
During count operation, the response delay time indicated by the following arithmetic expression occurs.
• Maximum response delay time = program scan time + two control cycles (20ms)
Program scan time
The I/O control mode of the CPU module is a refresh mode that performs batch processing prior to the start of program
operation. Therefore, I/O signal (X/Y) delay occurs. Direct access input (DX) and direct access output (DY) can be used to
minimize this delay.
For details on direct access input (DX) and direct access output (DY), refer to the following.
 MELSEC iQ-R CPU Module User's Manual (Application)
Control cycle (10ms)
A maximum delay of 20ms (one control cycle  2) occurs until the pulse input module reads the output signals (Y) and buffer
memory areas updated by the program and completes processing. There are also variations in the update timing of the input
signals (X) and buffer memory areas within the range of one control cycle.
1 FUNCTIONS
18
1.1 Count Operation