Mitsubishi Electric MELSEC iQ-R Series User Manual page 87

CH1 Count cycle change function selection
Set whether to use the count cycle change function.
For details on the count cycle change function, refer to the following.
Page 17 Count cycle change function
Setting value
0
1
If a value other than those shown in the above table is set, a count cycle change function selection setting error (error code:
1AD0H) occurs.
■Buffer memory addresses
The following shows the buffer memory addresses of this area.
Buffer memory name
CH Count cycle change function selection
CH Count cycle change function selection (when Q
series-compatible mode is used)
■Count cycle
Setting this area to Count cycle change function valid (1) sets the refreshing cycle for the following buffer memory areas to the
count cycle set by 'CH1 Count cycle setting value' (Un\G142).
• 'CH1 Sampling pulse number' (Un\G0)
• 'CH1 Accumulating count value' (Un\G2, Un\G3)
When this area is set to Count cycle change function invalid (0), the cycle becomes 1s.
■Enabling the setting
Turn on and off 'Operating condition setting request flag' (Y1).
■Default value
The default value is Count cycle change function invalid (0) for all channels.
CH1 Count cycle setting value
Set the count cycle for the sampling pulse number and accumulating count value.
For details on the count cycle change function, refer to the following.
Page 17 Count cycle change function
Setting value
0
1
2
3
If a value other than those shown in the above table is set, a count cycle setting value setting error (error code: 1AD1H)
occurs.
■Buffer memory addresses
The following shows the buffer memory addresses of this area.
Buffer memory name
CH Count cycle setting value
CH Count cycle setting value (when Q series-
compatible mode is used)
■Enabling the setting
Turn on and off 'Operating condition setting request flag' (Y1).
■Default value
The default value is 1s (0) for all channels.
Setting details
Count cycle change function invalid
Count cycle change function valid
CH1 CH2 CH3
141 173 205
23 55 87
Setting details
1s
100ms
200ms
500ms
CH1 CH2 CH3
142 174 206
24 56 88
CH4 CH5 CH6
237 269 301
119 151 183
CH4 CH5 CH6
238 270 302
120 152 184
Appendix 3 Buffer Memory Areas
CH7 CH8
333 365
215 247
A
CH7 CH8
334 366
216 248
APPX
85