Pci Express Configuration Submenu - Congatec conga-TS170 User Manual

Feature
MMIO 32 bit Resources Padding
PFMMIO 32 bit Resources Padding
11.4.21

PCI Express Configuration Submenu

Feature
PCI Express Clock Gating
DMI Link ASPM Processor Side
Port8xh Decode
Peer Memory Write Enable
Compliance Test Mode
PCIe-USB Glitch W/A
PCIe Function Swap
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Options Description
Disabled Select padd PCI MMIO 32-bit resources behind the bridge for hot-plug.
1 M
2 M
4 M
8 M
16 M
32 M
64 M
128 M
Disabled Select padd PCI MMIO 32-bit prefetchable resources behind the bridge for hot-plug.
1 M
2 M
4 M
8 M
16 M
32 M
64 M
128 M
Options Description
Disabled Enable or disable PCI Express clock gating for each root port.
Enabled
Disabled Enable or disable Active State Power Management of the DMI link on the processor side.
Enabled
Disabled Enable or disable Port8xh Decode
Enabled
Disabled Enable or disable Peer Memory Write
Enabled
Disabled Enable or disable Compliance Test Mode. Enable when using compliance load board.
Enabled
Disabled Enable or disable PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIe/PEG
Enabled port.
Disabled Enable or disable PCIe Function Swap. When disabled, it prevents PCIe root port function
Enabled swap.
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