ABB Relion 650 Series Operation Manual page 18

Section 1
Introduction
12
STCND
AND
L1L2
L2L3 AND
AND
L3L1
AND
L1N
AND
L2N
AND
L3N
VTSZ
OR
BLOCK
IEC99000557-TIFF V3 EN-US
Figure 2: Logic diagram example with intermediate output signals
IEC00000488-TIFF V1 EN-US
Figure 3: Logic diagram example with intermediate input signals
OR
OR
OR
BLOCFUNC
1MRK 500 128-UEN B
STZMPP
STNDL1L2
STNDL2L3
STNDL3L1
STNDL1N
STNDL2N
STNDL3N
STPE
STND
AND
BLK
99000557-2.vsd
650 series 2.2 IEC
Operation manual