ADLINK Technology NuDAQ PCI-9810 User Manual page 6

4.2 ADC Channel Enable Register .......................................... 20
4.3 ADC Clock Divisor Register ............................................... 21
4.4 Trigger Mode Register ....................................................... 22
4.5 Trigger Level Register........................................................ 23
4.6 Trigger Source Register..................................................... 24
4.7 Post Trigger Counter Register ........................................... 25
4.8 FIFO Status Register ......................................................... 26
4.9 FIFO Control Register........................................................ 27
4.10 Acquisition Enable Register ............................................... 28
4.11 Clock Source Register ....................................................... 28
4.12 High Level Programming ................................................... 29
4.13 Low Level Programming .................................................... 29
5 Operation Theory .............................................................. 31
5.1 A/D Conversion Procedure ................................................ 31
5.2 A/D Signal Source Control ................................................. 32
5.3 A/D Trigger Source Control................................................ 32
Trigger Sources ............................................................ 33
Simultaneous Trigger for Multiple Cards ...................... 34
Trigger Modes ............................................................... 35
5.4 A/D Clock Source Control .................................................. 37
A/D Clock Sources ........................................................ 37
Internal Pacer Clock ..................................................... 37
External Pacer Clock .................................................... 38
Multiple Cards Operation .............................................. 38
5.5 A/D Data Transfer .............................................................. 39
AD Data Transfer .......................................................... 39
Simultaneous Sampling of four AD Channels ............... 39
Total Data Throughput .................................................. 40
Maximum Acquiring Data Length .................................. 40
Bus-mastering Data Transfer ........................................ 41
Host Memory Operation ................................................ 41
Summary ...................................................................... 42
5.6 AD Data Format ................................................................. 43
6 C/C++ Library .................................................................... 45
6.1 Libraries Installation ........................................................... 45
6.2 Programming Guide........................................................... 45
Naming Convention ...................................................... 45
Data Types ................................................................... 46
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