Questionable Group (Fault Register) Structure - TDK-Lambda G10-500 User Manual

can be set by the user to enable SRQ (Service request) in case a condition change occurs. Event
registers latch condition registers state if the corresponding Enable registers are set to logical one.
Event registers remain set (latched) until the user reads the register, reading the register clears its
values until the next event.
Event register does not specify that a single condition event has occurred. In the period where an
event has occurred and user has read the value, the Condition register might change its value
multiple times.
7.3.2

Questionable Group (Fault Register) Structure

Questionable group fault register holds a snapshot of the actual faults state of the power supply at
a present time. If a fault occurs, the corresponding bit is set. If a fault is removed, the
corresponding bit is cleared. Some of the faults might quickly change their state (clear faults)
before the controlling PC detects it. Events can be stored in the Event register if the Enable register
allows it. Refer to General Status Register Commands (section 5.10.9) set. Table 7-7 describes bit
configuration of the questionable group fault register.
Bit Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Decimal Value
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
Table 7-7: Bit Configuration of Questionable Group Register
NOTE
Bit Symbol Description
- -
AC AC Fail
OTP Over Temperature Protection
FLD Fold Back Protection
OVP Over Voltage Protection
SO Shut Off (Daisy)
OFF Output Off
ILC Interlock
ENA Enable
UVP Under Voltage Protection
- -
- -
- -
- -
POFF Power Switch OFF
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