Intel Arria 10 SDI II User Manual page 43

2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Figure 19. Sequence of Video Standards for Triple-Rate and Multi-Rate Designs
Triple-Rate Designs
3G
Level A
Multi-Rate Designs
12G 8 Streams
Interleaved
For single-rate designs, only one video standard is tested:
• HD-SDI single-rate—HD
• 3G-SDI single-rate—3G Level A
If you turn on the Dynamic Tx Clock Switching parameter, only one video standard
is being tested with 2 different TX PHY reference clocks to demonstrate the switching:
• HD-SDI single-rate—HD
• 3G-SDI single-rate/triple-rate—3G Level A
• Multi-rate—12G 8 streams interleaved
Figure 20. Simulation Waveform
Video standard keeps switching
after obtaining lock signal
rx_std
align_locked
trs_locked
reconfig_count
expected_rcfgcount
The actual number of transceiver reconfigurations triggered
after every video standard vs. the expected number of
reconfigurations
A successful simulation ends with the following message:
#### TRANSMIT TEST COMPLETED SUCCESSFULLY! ####
#
#### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####
3G
HD
Level B
6G 8 Streams
Interleaved Level A
trs_locked from IP core
3'h3 3'h1 3'h2
4'h1 4'h1 4'h1
2'h1 2'h0 2'h1
SD HD
3G
HD
3'h0 3'h1
4'h0 4'h1
2'h0
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
3G
SD
Level A
SD
3'h0
4'h1 4'h0
2'h1
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