Intel Arria 10 SDI II User Manual page 16

Figure 9. Parallel Loopback with Simplex Mode Clocking Scheme
Top
RX Top
SDI RX System
Controller (RX)
(1) Block/Connection only required for parallel loopback with external VCXO designs.
(2) Block/Connection only required for parallel loopback without external VCXO designs.
(3) Block/Connection only required for triple-rate/multi-rate designs.
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Intel Arria 10 SDI II IP Core Design Example User Guide
16
SDI II
RX
Transceiver Transceiver
PHY Reset Native PHY
(RX)
RX
Reconfiguration
Management (3)
RX Reference
Clock
2 SDI II Design Example Detailed Description
Loopback Top
SDI II
Loopback
TX
FIFO
PFD (1)
Reclock (2)
Transceiver
Native PHY
Transceiver
(TX)
Arbiter
Management TX PLL
Clock Reference
Clock
UG-20076 | 2017.05.08
TX Top
SDI TX System
Transceiver
PHY Reset
Controller (TX)
TX PLL
TX PLL Reference Clock
TX Transceiver clkout
TX PLL Serial Clock
RX Reference Clock
RX Transceiver clkout
Management Clock