Intel Arria 10 SDI II User Manual page 15

2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Parallel Loopback with Simplex Mode
Figure 8. Parallel Loopback with Simplex Mode Block Diagram
Top
RX Top
SDI RX System
Controller (RX)
(1) Generate up/down control signal to on-board Si516 for clock synchronization purpose.
(2) Block/Connection only required for parallel loopback without external VCXO designs.
(3) Block/Connection only required for triple-rate/multi-rate designs.
(4) FVH video sync signals to LMH1983 for clock synchronization purpose.
SDI II
RX
Transceiver Transceiver
PHY Reset Native PHY
(RX)
RX
Reconfiguration
Management (3)
(4)
Loopback Top
Loopback
FIFO
PFD (1)
Reclock (2)
Transceiver
Native PHY
Transceiver
Arbiter (3)
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Intel Arria 10 SDI II IP Core Design Example User Guide
TX Top
SDI TX System
SDI II
TX
Transceiver
PHY Reset
(TX) Controller (TX)
TX PLL
Parallel Data
Serial Data
Control/Status
Avalon-MM
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