Intel Arria 10 SDI II User Manual page 27

2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Clock Signal Name in Design
rx_core_refclk
Description
• Parallel loopback with external VCXO
— For this design example, the minimum clock
frequency of 148.5 MHz is used in the multi-rate
design example. For single-rate and triple-rate design
examples, a higher reference clock (270 MHz) is used
instead.
— Using a higher clock frequency would require a
modification of the RX CDR reference clock value in
the Arria 10 Native PHY Transceiver parameter editor.
For triple or multi-rate modes, you need to modify
the reference clock value for every profiles.
• Parallel loopback without external VCXO and Serial
loopback
— The minimum clock frequency is 148.5 MHz.
— Using a higher clock frequency would require a
modification of the RX CDR reference clock value in
the Arria 10 Native PHY Transceiver parameter editor.
For triple or multi-rate modes, you need to modify
the reference clock value for every profiles.
Note: Do not share the TX PLL reference clock with the RX
transceiver reference clock for a parallel loopback
design. In parallel loopback designs, the TX PLL
clock is tuned to match the RX recovered clock
frequency.
SDI RX core reference clock.
The required frequency is 148.5 MHz. This clock must be a
free-running clock.
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Intel Arria 10 SDI II IP Core Design Example User Guide
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