Intel Arria 10 SDI II User Manual page 32

sdi_tx_ln_b
sdi_tx_vpid_overwrit
e
sdi_tx_line_f0
sdi_tx_line_f1
sdi_tx_vpid_byte1
sdi_tx_vpid_byte2
sdi_tx_vpid_byte3
sdi_tx_vpid_byte4
sdi_tx_vpid_byte1_b
sdi_tx_vpid_byte2_b
sdi_tx_vpid_byte3_b
sdi_tx_vpid_byte4_b
sdi_rx_coreclk_is_nt
sc_paln
sdi_tx_datavalid
sdi_rx_align_locked
sdi_rx_trs_locked
sdi_rx_clkout_is_nts
c_paln
sdi_rx_format
sdi_rx_ap
sdi_rx_eav
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
32
Other SDI Video Protocol Interfaces
Input 11*N
Input 1
Input 11*N
Input 11*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 8*N
Input 1
Output 1
Output 1
Output N
Output 1
Output 4*N
Output N
Output N
2 SDI II Design Example Detailed Description
LN insertion in the data stream when
= 1.
sdi_tx_enable_ln
Only for 3G level B, 6G 8 streams interleaved, and 12G
16 streams interleaved.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Enable this signal to overwrite the existing payload ID
embedded in the data stream.
Indicates the line number to be inserted with the payload
ID.
Payload ID byte to be inserted in the payload ID field.
To indicate whether
rx_coreclk
MHz:
• 0: 148.5 MHz
• 1: 148.35 MHz
Data valid signal generated from SDI TX core. The timing
(H: High, L: Low) is synchronous to
and has the following settings:
• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H (for single-rate) and 1H 1L (triple-rate/
multi-rate)
• 3G/6G/12G-SDI = H
Alignment locked indicating the IP core has spotted a
TRS and word alignment performed.
TRS locked indicating the IP core has spotted six
consecutive TRS with same timing.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Indicates that the receiver is receiving video rate at
integer or fractional frame rate:
• 0: Integer frame rate
• 1: Fractional frame rate
Received video transport format. Refer to the SDI II IP
User Guide for the encoding value.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Active picture interval timing signal. This signal asserts
when the active picture interval is active.
Receiver output signal that indicates current TRS is EAV.
This signal is asserted at the fourth word of TRS, which is
the XYZ word.
UG-20076 | 2017.05.08
is 148.5 MHz or 148.35
tx_vid_clkout
continued...