Intel Arria 10 SDI II User Manual page 36

sdi_rx_h
sdi_rx_format
sdi_rx_clkout_is_nts
c_paln
sdi_tx_datain
sdi_tx_datain_valid
sdi_tx_trs
sdi_tx_std
vcoclk_up
vcoclk_down
pll_locked
pll_reconfig_readdat
a
pll_reconfig_waitreq
uest
pll_reconfig_write
pll_reconfig_read
pll_reconfig_writeda
ta
pll_reconfig_address
Table 14. Transceiver Arbiter Signals
Signal
clk
reset
rx_rcfg_en
tx_rcfg_en
rx_rcfg_ch
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
36
SDI Related Signals
Input 1
Input 4
Input 1
Output 20*N
Output 1
Output 1
Output 3
Voltage Control Signals for On-board Si516
Output 1
Output 1
fPLL Reconfiguration Signals
Input 1
Input 32
Input 1
Output 1
Output 1
Output 32
Output 10
Direction Width
On-board Oscillator Signals
Input 1
Input 1
Input 1
Input 1
Input 2
2 SDI II Design Example Detailed Description
Horizontal blanking interval timing signal extracted from
SDI RX core.
Received video transport format.
Indication from SDI RX core that the receiver is receiving
video rate at integer or fractional frame rate.
Parallel video data input to SDI TX core.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Data valid for the transmitter parallel data to SDI TX
core.
Transmitter TRS input to indicate that the current word is
a TRS to SDI TX core.
Indicates the desired transmit video standard to SDI TX
core.
Voltage up signal to Si516 to increase the voltage.
Voltage down signal to Si516 to decrease the voltage.
PLL lock status signal.
Reconfiguration interface signals to fPLL Avalon-MM
interface.
Description
Reconfiguration clock. This clock should be sharing the
same clock as reconfiguration management blocks.
Reset signal. This reset should be sharing the same reset
as reconfiguration management blocks.
RX reconfiguration enable signal.
TX reconfiguration enable signal.
Indicates which channel to be reconfigured on RX.
Always assign to 2'b00 for SDI case.
UG-20076 | 2017.05.08
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