Intel Arria 10 SDI II User Manual page 4

Figure 2. Directory Structure for the Design Examples
quartus
sdi_ii_a10_demo.qpf
sdi_ii_a10_demo.qsf
Table 1. Other Generated Files in RTL Folder
Folders
vid_pattgen
loopback
du
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
4
hwtest
(for serial loopback design)
db/qdb
tpg.ctrl.tcl (optional)
/sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/jtag.sdc
/pattgen_ctrl.qsys
<qsys generated folder>
/loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
/pfd/clock_crossing.v
/pfd/pfd.sdc
/pfd/pfd.v
/reclock/sdi_reclock.v
/reclock/pid_controller.v
/du_top.v
/sdi_ii_rx_rcfg_a10.sv
/rcfg_sdi_cdr.sv
1 SDI II Design Example Quick Start Guide
<Design Example>
simulation
aldec
cadence
mentor
synopsys
testbench
Files
(optional)
(optional)
(optional)
(optional)
(optional)
(optional)
(optional)
UG-20076 | 2017.05.08
rtl
sdi_ii_a10_demo.v
sdi_ii_a10_demo.sdc
edge_detector.sv
clock_heartbeat.sv
a10_reconfig_arbiter.sv (optional)
clk_ctrl.qsys (optional)
pll_148.qsys (optional)
vid_pattgen (for serial loopback design)
loopback (for parallel loopback design)
du (for duplex mode design)
rx (for simplex mode design)
tx (for simplex mode design)
<clk_ctrl.qsys generated>(optional)
<pll_148 qsys generated> (optional)
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