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2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Table 6.
Device Under Test (DUT) Components
Design Component
SDI II IP Core
Transceiver Native PHY IP Core
Transceiver PHY Reset Controller
RX Reconfiguration Management
•
TX
— The TX core receives the video data from the top level and encodes the
necessary information, (e.g. line number (LN), cyclical redundancy check
(CRC), payload ID), into the data stream(s).
— In a multi-rate design, the TX core oversamples the received data up to
11.88 Gbps data rate for every video standard. Specify the assignment of
the parallel data interface (
on the 11.88 Gbps data rate settings.
•
RX
— The RX core receives the parallel data from the Transceiver Native PHY IP
core and decodes information. This information includes descrambling,
realigning data, and extracting the necessary information for user.
— For a multi-rate design, due to the difference in data widths recovered for
different video standards, rearrange
transceiver before passing the data back to the protocol block.
•
TX
Hard transceiver block that receives parallel data from the SDI II IP core and
serializes the data before transmission.
— For HD/3G-SDI single-rate and triple-rate designs, enable the simplified
data interface option to connect parallel data directly to the
signal of the SDI II IP core.
— For a multi-rate design, disable this option due to the limitation in the
12G-SDI transceiver PHY settings.
•
RX
Hard transceiver block that receives serial data from an external video
source.
— For HD/3G-SDI single-rate and triple-rate designs, enable the simplified
data interface option to connect parallel data directly to the
signal of SDI II IP core.
— For a multi-rate design, disable this option due to the limitation in the
12G-SDI transceiver PHY settings.
You must connect the
rx_analogreset_ack
the RX Reconfiguration Management module to indicate that the transceiver is
in reset.
Note: For the duplex mode transceiver (SDI triple-rate parallel loopback with
external VCXO design example), generate a dummy RX only PHY
(
) to get the transceiver configuration files
sdi_rx_phy.qsys
(
,
*_CFG0.sv
*_CFG1.sv
configuration files from the duplex mode transceiver may contain some
TX registers. You don't need to reconfigure the registers because only the
SDI RX core requires transceiver reconfiguration.
•
TX
— The reset input of this controller is triggered from the top level.
— The controller generates the corresponding analog and digital reset signal
to the Transceiver Native PHY block, according to the reset sequencing
inside the block.
— Use the
output signal from the block as a reset signal to the TX
tx_ready
core to indicate that the transceiver is up and running, and ready to
receive data from the core.
•
RX
— The reset input of this controller is triggered by the SDI II IP core.
— The controller generates the corresponding analog and digital reset signal
to the Transceiver Native PHY block according to the reset sequencing
inside the block.
RX transceiver reconfiguration management block that reconfigures the
Transceiver Native PHY block to receive different data rates from SD-SDI to 12G-
SDI standards.
®
Intel
Description
) to the transceiver based
tx_parallel_data
rx_parallel_data
output signal from this block to
, ...) for RX reconfiguration. The generated
®
Arria
10 SDI II IP Core Design Example User Guide
from the
tx_dataout
rx_datain
continued...
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