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Design Component
TX Reconfiguration Management
TX PLL/TX PLL Alt
Table 7.
Loopback Components
Component
Loopback FIFO
Phase Frequency Detector (PFD)
Reclock
®
®
Intel
Arria
10 SDI II IP Core Design Example User Guide
24
To indicate the status of the transceiver, connect
from the transceiver to this block.
rx_analogreset_ack
TX PLL or transceiver reconfiguration management block that reconfigures the TX
PLL or Transceiver Native PHY block to change the TX clock dynamically for
switching between integer and fractional frame rates.
The block requires
tx_cal_busy
from the transceiver, and the PLLs to indicate the status of the transceiver in a
TX PLL switching design.
Transmitter PLL block that provides the serial fast clock to Transceiver Native
PHY.
•
For TX PLL switching design, TX PLL is always configured to generate integer
frame rate while TX PLL Alt is configured to generate fractional frame rate.
•
For TX PLL reference clock switching design, TX PLL is configured to have
reference clock 0 to generate integer frame rate and reference clock 1 to
generate fractional frame rate.
•
For single-rate and triple-rate designs, this PLL can be either CMU PLL or
fPLL.
•
For multi-rate designs, CMU PLL is not recommended for 12G data rate. Use
fPLL instead.
Move the TX PLL out from the TX top if you want to merge the PLL between
multiple channels.
This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data
transmission across asynchronous clock domains—the receiver recovered clock
and transmitter clock out.
•
The receiver sends the decoded RX data to the transmitter through this FIFO
buffer.
•
When the receiver locks, the RX data is written to the FIFO buffer.
•
The transmitter starts reading, encoding, and transmitting the data when half
of the FIFO buffer is filled.
You require this soft PFD block when you use the Arria 10 GX FPGA development
kit on-board Si516 VCXO for a parallel loopback design.
•
This block compares the phase between the receiver and transmitter parallel
clocks, and generates an up or down signal, that connects to the Si516 VCXO.
•
These up/down signals control the voltage of the VCXO, so that the
frequencies of both clock domains can be tuned as close as possible to each
other.
Note: Applicable only for parallel loopback with external VCXO designs.
The parallel loopback without external VCXO design requires this module. Similar
to the PFD block, this block compares the phase between the receiver and
transmitter parallel clocks.
The output interfaces of this block connect to the reconfiguration Avalon
Memory-Mapped (Avalon-MM) interfaces of an fPLL. If there is any difference in
the frequencies between the clock domains, this module generates the necessary
signals to reconfigure the fPLL to match the clock frequencies as close as
possible.
Note: Applicable only for parallel loopback without external VCXO designs.
2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Description
rx_cal_busy
,
, and
pll_cal_busy
tx_analogreset_ack
Description
and
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