Intel Arria 10 SDI II User Manual page 20

Figure 13. Serial Loopback with Simplex Mode Clocking Scheme
Top
RX Top
SDI RX System
Controller (RX)
(1) Block/Connection only required for triple-rate/multi-rate designs.
(2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs.
(3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.
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Intel Arria 10 SDI II IP Core Design Example User Guide
20
SDI II
RX
Transceiver Transceiver
PHY Reset Native PHY
(RX)
(1)
RX
Reconfiguration
Management (1)
RX Reference
Clock
2 SDI II Design Example Detailed Description
Video Pattern
Generator
Pattern Generator Control
Pattern Generator
Control PIO
JTAG to Avalon
Master Bridge
Transceiver
Native PHY
TX Reconfiguration
Transceiver Arbiter
Management
(1), (2)
Management
Clock
UG-20076 | 2017.05.08
TX Top
SDI TX System
SDI II
TX
Transceiver
PHY Reset
(TX) Controller (TX)
(2)
(3)
TX TX
(3)
PLL PLL
(2), (3)
Alt (2)
TX PLL TX PLL Alt
Reference Reference
Clock Clock (2), (3)
TX PLL Reference Clock
TX Transceiver clkout
TX PLL Serial Clock
RX Reference Clock
RX Transceiver clkout
Management Clock