Related Manuals for Intel Arria 10 SDI II
Summary of Contents for Intel Arria 10 SDI II
- Page 1 ® ® Intel Arria 10 SDI II IP Core Design Example User Guide ® ® Updated for Intel Quartus Prime Design Suite: 17.0 Subscribe UG-20076 | 2017.05.08 Send Feedback Latest document on the web: HTML...
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Page 2: Table Of Contents
2.8 Simulation Testbench.................... 41 A SDI II IP Core Design Example User Guide Archives............44 B Revision History for SDI II IP Core Design Example User Guide........45 ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... -
Page 3: Sdi Ii Design Example Quick Start Guide
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. - Page 4 /sdi_ii_makeframe.v /sdi_ii_patho_gen.v /jtag.sdc /pattgen_ctrl.qsys <qsys generated folder> loopback /loopback_top.v /fifo/sdi_ii_ed_loopback.sdc /fifo/sdi_ii_ed_loopback.v (optional) /pfd/clock_crossing.v (optional) /pfd/pfd.sdc (optional) /pfd/pfd.v (optional) /reclock/sdi_reclock.v (optional) /reclock/pid_controller.v /du_top.v (optional) /sdi_ii_rx_rcfg_a10.sv (optional) /rcfg_sdi_cdr.sv continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 5 (Quartus Prime Pro Edition) /tx_pll_alt.ip (optional) <qsys generated folder> Table 2. Other Generated Files in Simulation Folder Folders Files aldec /aldec.do /rivierapro_setup.tcl cadence /cds.lib /hdl.var /ncsim.sh /ncsim_setup.sh continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 6: Hardware And Software Requirements
1.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design examples: ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... -
Page 7: Generating The Design
• Intel Quartus Prime (for hardware testing) • ModelSim* - Intel FPGA Edition, ModelSim-SE, NCSim (Verilog only), Riviera-Pro, or VCS (Verilog only)/VCS-MX simulator 1.3 Generating the Design Use the SDI II parameter editor in the Quartus Prime software to generate the design examples. -
Page 8: Simulating The Design
#### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! #### 1.5 Compiling and Testing the Design Compile Design Test Design Set Up Hardware Program Device in Quartus Prime in Hardware Software ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... -
Page 9: Connection And Settings Guidelines
Note: For parallel loopback designs, you may need to switch the Si516_FS (SW6.3) at the back of the board if you are switching between fractional frame rate and integer frame rate video format. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 10 RZQ_B2K • ON for setting RZQ resistor of Bank 2K to 99.17 ohm • OFF for setting RZQ resistor of Bank 2K to 240 ohm (Default position) ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 11: Design Limitations For Serial Loopback Design
• Pin 1–2 = SDI mode • Pin 2–3 = IP mode Related Links Intel Arria 10 FPGA Development Kit User Guide 1.5.2 Design Limitations for Serial Loopback Design The serial loopback design example has the following limitations: ® ®... - Page 12 To allow segmented frame video format (1080sF30, 1080sF25) and interlaced video format (1080i60, 1080i50) to be correctly differentiated in the external analyzer, Payload ID has to be inserted in the serial loopback design. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 13: Sdi Ii Design Example Detailed Description
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. -
Page 14: Parallel Loopback Design Examples
(single-rate and triple-rate), use the only 148.5 MHz on-board oscillator as the TX PLL reference clock. For the RX reference clock, use a 270 MHz clock from another on- board oscillator. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 15 (2) Block/Connection only required for parallel loopback without external VCXO designs. Serial Data (3) Block/Connection only required for triple-rate/multi-rate designs. Control/Status (4) FVH video sync signals to LMH1983 for clock synchronization purpose. Avalon-MM ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 16 (1) Block/Connection only required for parallel loopback with external VCXO designs. RX Reference Clock (2) Block/Connection only required for parallel loopback without external VCXO designs. RX Transceiver clkout (3) Block/Connection only required for triple-rate/multi-rate designs. Management Clock ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 17 (2) Block/Connection only required for parallel loopback without external VCXO designs. Control/Status (3) Block/Connection only required for triple-rate/multi-rate designs. Avalon-MM (4) FVH video sync signals to LMH1983 for clock synchronization purpose. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 18: Serial Loopback Design Examples
(2) Block/Connection only required for parallel loopback without external VCXO designs. Management Clock (3) Block/Connection only required for triple-rate/multi-rate designs. 2.2 Serial Loopback Design Examples The serial loopback design examples demonstrate simplex and duplex channel modes. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 19 (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. Serial Data (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs. Control/Status Avalon-MM ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 20 (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. RX Transceiver clkout (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs. Management Clock ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 21 Serial Data (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. Control/Status (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs. Avalon-MM ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 22: Design Components
(3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs. Management Clock 2.3 Design Components The SDI II IP core design examples require the following components. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 23 RX Reconfiguration Management RX transceiver reconfiguration management block that reconfigures the Transceiver Native PHY block to receive different data rates from SD-SDI to 12G- SDI standards. continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 24 Note: Applicable only for parallel loopback without external VCXO designs. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 25: Clocking Scheme Signals
Signal Name in Design Description TX PLL Refclock TX PLL reference clock, of any frequency that is divisible by tx_pll_refclk the transceiver for that data rate. continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 26 Only a single reference clock frequency is required to support both integer and fractional frame rates. It must be a free running clock connected to the transceiver clock pin. continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 27 RX recovered clock frequency. SDI RX core reference clock. rx_core_refclk The required frequency is 148.5 MHz. This clock must be a free-running clock. continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 28: Interface Signals
On-board Oscillator Signals Input 100 MHz clock for reconfiguration Avalon-MM interfaces. clk_fpga_b2_p Input 100 MHz dedicated transceiver reference clock. pcie_ob_refclk_p Input 270 MHz dedicated transceiver reference clock. refclk_dp_p continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 29 V sync signal LMH1983 on Nextera daughter card. fmcb_la_tx_p14 Output H sync signal LMH1983 on Nextera daughter card. fmcb_la_tx_n14 Output Power-down signal LMH1983 on Nextera daughter card. fmcb_la_tx_p15 ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 30 3'b010 3G-SDI Level B • 3'b101: 6G-SDI 4 Streams Interleaved • 3'b100: 6G-SDI 8 Streams Interleaved • 3'b111: 12G-SDI 8 Streams Interleaved • 3'b110: 12G-SDI16 Streams Interleaved continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 31 Enable LN insertion for all SDI video standards, except sdi_tx_enable_ln SD-SDI. Input 11*N LN insertion in the data stream when sdi_tx_ln = 1. sdi_tx_enable_ln Note: N = 4 (multi-rate design) or 1 (triple-rate design) continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 32 Output Receiver output signal that indicates current TRS is EAV. sdi_rx_eav This signal is asserted at the fourth word of TRS, which is the XYZ word. continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 33 TX transceiver status. gxb_tx_ready Output Calibration status signal from RX transceiver. gxb_rx_cal_busy Output Calibration status signal from TX transceiver. gxb_tx_cal_busy Output TX PLL lock status. tx_pll_locked continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 34 Input rx_rcfg_waitrequest Output rx_rcfg_write Output rx_rcfg_read Output rx_rcfg_address Output rx_rcfg_writedata Input Reconfiguration interface signals from TX reconfiguration tx_rcfg_readdata management module to transceiver arbiter Input tx_rcfg_waitrequest continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 35 Note: N = 4 (multi-rate design) or 1 (triple-rate design) Input Frame locked status signal from SDI RX core. sdi_rx_frame_locked Input Data valid signal generated from SDI TX core. sdi_tx_dataout_valid continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 36 RX reconfiguration enable signal. rx_rcfg_en Input TX reconfiguration enable signal. tx_rcfg_en Input Indicates which channel to be reconfigured on RX. rx_rcfg_ch Always assign to 2'b00 for SDI case. continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 37 Calibration status signal from TX transceiver. tx_cal_busy Output Calibration status signal to RX transceiver PHY reset rx_reconfig_cal_busy control. Output Calibration status signal from TX transceiver PHY reset tx_reconfig_cal_busy control. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 38 The payload ID output signal to be connected to vpid_byte2 input signal on TX/Du top. sdi_tx_vpid_byte2 Input The payload ID output signal to be connected to vpid_byte3 input signal on TX/Du top. sdi_tx_vpid_byte3 continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 39: Video Pattern Generator Parameters
Output control signal from PIO to control the video pattgen_ctrl_pio_out pattern generator. _port 2.6 Video Pattern Generator Parameters Customize the video pattern generator parameters according to your design. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... -
Page 40: Hardware Setup
Indicates the receiver video standard: • 000: SD-SDI • 001: HD-SDI • 010: 3G Level B • 011: 3G Level A • 100: 6G 8 Streams Interleaved continued... ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... -
Page 41: Simulation Testbench
(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for TX PLL switching designs. Control/Status (3) Block/Connection only required for TX PLL reference clock switching designs. Avalon-MM ® ® Intel Arria 10 SDI II IP Core Design Example User Guide... - Page 42 TX Checker This checker verifies if the TX serial data contains a valid TRS signal. ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
- Page 43 A successful simulation ends with the following message: #### TRANSMIT TEST COMPLETED SUCCESSFULLY! #### #### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! #### ® ® Intel Arria 10 SDI II IP Core Design Example User Guide...
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Page 44: A Sdi Ii Ip Core Design Example User Guide Archives
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. -
Page 45: B Revision History For Sdi Ii Ip Core Design Example User Guide
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.