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2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
tx_rcfg_write
tx_rcfg_read
tx_rcfg_address
tx_rcfg_writedata
tx_fpll_rcfg_write
tx_fpll_rcfg_read
tx_fpll_rcfg_writeda
ta
tx_fpll_rcfg_address
tx_fpll_rcfg_readdat
a
tx_fpll_rcfg_waitreq
uest
Table 13.
Loopback Top Signals
Signal
sdi_tx_clkout
sdi_rx_clkout
sdi_reclk_sysclk
sdi_rx_rst_proto
sdi_reclk_rst
sdi_rx_dataout
sdi_rx_dataout_valid
sdi_rx_std
sdi_rx_trs
sdi_rx_trs_locked
sdi_rx_frame_locked
sdi_tx_dataout_valid
Transceiver Reconfiguration Interfaces
Output
1
Output
1
Output
10
Output
32
Input
1
Input
1
Input
32
Input
10
Output
32
Output
1
Direction
Width
Clocks
Input
1
Input
1
Input
1
Resets
Input
1
Input
1
SDI Related Signals
Input
20*N
Input
1
Input
3
Input
N
Input
N
Input
1
Input
1
Reconfiguration interface signals to fPLL Avalon-MM
interface.
Description
TX transceiver recovered parallel clock for video data.
RX transceiver recovered parallel clock for video data.
Input clock for reclock module (without external VCXO
solution). This clock should be the same as fPLL
.
reconfig_clk
Reset signal from SDI RX core to indicate that the
protocol is currently held in reset.
Reset signal to reclock module (without external VCXO
solution).
Receiver recovered parallel video data.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Data valid signal generated from SDI RX core.
Received video standard from SDI RX core.
Receiver output signal from SDI II IP core that indicates
current word is TRS.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
TRS locked status signal from SDI RX core.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Frame locked status signal from SDI RX core.
Data valid signal generated from SDI TX core.
®
®
Intel
Arria
10 SDI II IP Core Design Example User Guide
continued...
35
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