Intel Arria 10 SDI II User Manual page 30

Table 12. RX/TX/DU Top Signals
Signal
rx_cdr_refclk
rx_core_refclk
tx_pll_refclk
tx_pll_refclk_alt
rx_rcfg_mgmt_clk
tx_rcfg_mgmt_clk
rx_vid_clkout
tx_vid_clkout
tx_resetn
rx_resetn
tx_rcfg_mgmt_resetn
rx_rcfg_mgmt_resetn
sdi_rx_rst_proto_out
Video Signal Interfaces (Interface with Video Image and Processing (VIP) Components)
rx_vid_data
rx_vid_datavalid
rx_vid_std
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
30
Direction Width
Clocks
Input 1
Input 1
Input 1
Input 1
Input 1
Input 1
Output 1
Output 1
Reset
Input 1
Input 1
Input 1
Input 1
Output 1
Output 20*N
Output 1
Output 3
2 SDI II Design Example Detailed Description
Description
RX transceiver reference clock. This clock must be a free-
running clock.
SDI RX core clock. This clock must be a free-running
clock.
TX PLL reference clock. This clock must be a free-running
clock.
Secondary TX PLL reference clock. This clock must be a
free-running clock.
RX reconfiguration management clock, Avalon-MM
interface clock, and PHY reset control input clock. This
clock must be a free-running clock.
TX reconfiguration management clock, and Avalon-MM
interface clock, and PHY reset control input clock. This
clock must be a free-running clock.
RX transceiver recovered parallel clock for video data.
TX transceiver recovered parallel clock for video data.
TX core and PHY reset signal.
RX core and PHY reset signal.
TX reconfiguration reset signal.
RX reconfiguration reset signal.
Reset signal generated to reset the receiver downstream
protocol logic. This generated reset signal is synchronous
to clock domain.
rx_vid_clkout
Receiver parallel video data out.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Data valid signal generated from SDI RX core. The timing
must be synchronous to
rx_vid_clkout
following settings:
• SD-SDI: 1H 4L 1H 5L
• HD/3G/6G/12G-SDI: H
Received video standard.
• 3'b000: SD-SDI
• 3'b001: HD-SDI
• 3'b011: 3G-SDI Level A
• 3'b010 3G-SDI Level B
• 3'b101: 6G-SDI 4 Streams Interleaved
• 3'b100: 6G-SDI 8 Streams Interleaved
• 3'b111: 12G-SDI 8 Streams Interleaved
• 3'b110: 12G-SDI16 Streams Interleaved
UG-20076 | 2017.05.08
and has the
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