Intel Arria 10 SDI II User Manual page 26

Clock
TX PLL Alt Refclock
TX Transceiver Clockout
TX PLL Serial Clock
RX Refclock
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Intel Arria 10 SDI II IP Core Design Example User Guide
26
Signal Name in Design
tx_pll_refclk_alt
tx_vid_clkout
tx_serial_clk
rx_cdr_refclk
2 SDI II Design Example Detailed Description
Description
Note: You must connect this clock to a dedicated
transceiver reference clock pin.
• Parallel loopback with external VCXO
— Use a minimum clock frequency of 148.5 MHz
(single-rate/triple-rate) or 297 MHz (multi-rate) to
meet jitter performance specification.
— Using a higher clock frequency would require a
modification of the TX PLL reference clock value in
the TX PLL parameter editor.
• Parallel loopback without external VCXO
— The recommended frequency is 100 MHz.
• Serial loopback
— For this design, the TX PLL refclock is configured to
generate clock for integer frame rate.
— The minimum clock frequency is 148.5 MHz (single-
rate/triple-rate) or 297 MHz (multi-rate) to meet
jitter performance specification.
— Using a higher clock frequency would require a
modification of the TX PLL reference clock value in TX
PLL parameter editor.
Second TX PLL reference clock which can be any clock
frequency that is divisible by transceiver for that data rate.
This clock must be connected to a dedicated transceiver
reference clock pin.
• Serial loopback
— For this design example, TX PLL alt refclock is
configured to generate clock for fractional frame rate.
— The minimum clock frequency is 148.35 MHz (single-
rate/triple-rate) or 297.7 MHz (multi-rate) to meet
jitter performance specification.
— Using a higher clock frequency would require a
modification of the TX PLL reference clock value in
the TX PLL parameter editor.
Recovered clock from the transceiver.
• HD-SDI single rate
— 74.25 MHz (default)
— 74.1758 MHz (for the Dynamic TX clock switching
feature when you transmit video format with
fractional frame rate)
• 3G-SDI single rate, triple rate or multi rate
— 148.5 MHz (default)
— 148.35 MHz (for the Dynamic TX clock switching
feature when you transmit video format with
fractional frame rate)
Serial fast clock generated by TX PLL. The clock frequency is
set based on the data rate.
Transceiver clock data recovery (CDR) reference clock, of
any frequency that is divisible by the transceiver for that
data rate. Only a single reference clock frequency is
required to support both integer and fractional frame rates.
It must be a free running clock connected to the transceiver
clock pin.
UG-20076 | 2017.05.08
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