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2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Video Signal Interfaces (Interface with Video Image and Processing (VIP) Components)
rx_vid_locked
rx_vid_hsync
rx_vid_vsync
rx_vid_f
rx_vid_trs
tx_vid_data
tx_vid_datavalid
tx_vid_std
tx_vid_trs
sdi_tx_enable_crc
sdi_tx_enable_ln
sdi_tx_ln
Output
1
Output
N
Output
N
Output
N
Output
N
Output
20*N
Input
1
Input
3
Input
1
Other SDI Video Protocol Interfaces
Input
1
Input
1
Input
11*N
Frame locked indicates that the IP core has spotted
multiple frames with the same timing.
Horizontal blanking interval timing signal. The receiver
asserts this signal when the horizontal blanking interval
is active.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Vertical blanking interval timing signal. The receiver
asserts this signal when the vertical blanking interval is
active.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Field bit timing signal. This signal indicates which video
field is currently active. For interfaced frame, 0 means
first field (F0) while 1 means second field (F1). For
progressive frame, the value is always 0.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
On-board SDI TX cable driver slew rate control.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Receiver output signal that indicates current word is
timing reference signal (TRS). This signal asserts at the
first word of 3FF 000 000 TRS.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
Transmitter parallel data valid. The timing (H: High, L:
Low) must be synchronous to
and has the following settings:
•
SD-SDI = 1H 4L 1H 5L
•
HD-SDI = H (for single-rate) and 1H 1L (triple-rate/
multi-rate)
•
3G/6G/12G-SDI = H
Indicates the desired transmit video standard.
•
3'b000: SD-SDI
•
3'b001: HD-SDI
•
3'b011: 3G-SDI Level A
•
3'b010 3G-SDI Level B
•
3'b101: 6G-SDI 4 Streams Interleaved
•
3'b100: 6G-SDI 8 Streams Interleaved
•
3'b111: 12G-SDI 8 Streams Interleaved
•
3'b110: 12G-SDI16 Streams Interleaved
Transmitter TRS input.
For use in LN, CRC, or payload ID insertion. Assert on
the first word of both end of active video (EAV) TRS and
start of active video (SAV) TRS.
Enable CRC insertion for all SDI video standards, except
SD-SDI.
Enable LN insertion for all SDI video standards, except
SD-SDI.
LN insertion in the data stream when
= 1.
sdi_tx_enable_ln
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
®
®
Intel
Arria
10 SDI II IP Core Design Example User Guide
clock domain
tx_pclk
continued...
31
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