Intel Arria 10 SDI II User Manual page 19

2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Serial Loopback with Simplex Mode
Figure 12. Serial Loopback with Simplex Mode Block Diagram
Top
RX Top
SDI RX System
Controller (RX)
(1) Block/Connection only required for triple-rate/multi-rate designs.
(2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs.
(3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.
SDI II
RX
Transceiver Transceiver
PHY Reset Native PHY
(RX)
RX
Reconfiguration
Management (1)
Video Pattern
Generator
Pattern Generator Control
Pattern Generator
Control PIO
JTAG to Avalon
Master Bridge
(1) (2)
(1) (2)
Transceiver Arbiter
(1) (2)
(1), (2)
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
TX Top
SDI TX System
SDI II
TX
Transceiver Transceiver
Native PHY PHY Reset
(TX) Controller (TX)
(3)
TX Reconfiguration
TX TX
(2)
Management
PLL PLL
(2)
(2), (3)
Alt (2)
Parallel Data
Serial Data
Control/Status
Avalon-MM
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