Intel Arria 10 SDI II User Manual page 42

Figure 18. Duplex Mode Simulation Testbench Block Diagram
Top
Duplex Top
SDI Duplex System
Management (1)
(1) Block/Connection only required for triple-rate/multi-rate designs.
(2) Block/Connection only required for TX PLL switching designs.
(3) Block/Connection only required for TX PLL reference clock switching designs
Table 17. Testbench Components
Component
Testbench Control
RX Checker
TX Checker
® ®
Intel Arria 10 SDI II IP Core Design Example User Guide
42
SDI II
Duplex
Transceiver Transceiver
PHY Reset Native PHY
Controller (RX) (Duplex)
RX TX Reconfiguration
Reconfiguration Management
(2), (3)
This block controls the test sequence of the simulation and generates the
necessary stimulus signals to the TX and video pattern generator blocks.
This checker detects the
the actual number of transceiver reconfigurations performed versus the expected
number.
This checker verifies if the TX serial data contains a valid TRS signal.
2 SDI II Design Example Detailed Description
Transceiver
PHY Reset
Controller (TX)
(3)
(1), (2)
TX TX
(2)
PLL PLL
(2)
Alt (2)
Description
signal from the RX protocol and compares
trs_locked
UG-20076 | 2017.05.08
Video Pattern
Generator
Testbench Control
TX Checker
RX Checker
Transceiver Arbiter
(1), (2)
Parallel Data
Serial Data
Control/Status
Avalon-MM