General Description; Analog Transceiver; Serial Interface Engine (Sie); Endpoint Ram (Ep_Ram) - NXP Semiconductors LPC1311 User Manual

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10.6 General description

The architecture of the USB device controller is shown below in
register
interface
(APB slave)
USB DEVICE
BLOCK
Fig 16. USB device controller block diagram

10.6.1 Analog transceiver

The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX
sends/receives the bi-directional USB_DP and USB_DM signals of the USB bus.

10.6.2 Serial Interface Engine (SIE)

The SIE implements the full USB protocol layer. It is completely hardwired for speed and
needs no firmware intervention. It handles transfer of data between the endpoint buffers in
EP_RAM and the USB bus. The functions of this block include: synchronization pattern
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.

10.6.3 Endpoint RAM (EP_RAM)

Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for
this purpose is called the EP_RAM. Each endpoint has a reserved space in the EP_RAM.
The total EP_RAM space is fixed. All endpoints are realized automatically.

10.6.4 EP_RAM access control

The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the
sources that can access it: the CPU (via the Register Interface) and the SIE.
UM10375
User manual
BUS
MASTER
INTERFACE
EP_RAM
REGISTER
ACCESS
INTERFACE
CONTROL
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 June 2011
Chapter 10: LPC13xx USB device controller
SERIAL
INTERFACE
ENGINE
UM10375
Figure 16.
V
BUS
USB_CONNECT
USB_DP
USB_DM
© NXP B.V. 2011. All rights reserved.
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