NXP Semiconductors LPC1313 Manuals

Manuals and User Guides for NXP Semiconductors LPC1313. We have 1 NXP Semiconductors LPC1313 manual available for free PDF download: User Manual

NXP Semiconductors LPC1313 User Manual (368 pages)

ARM Cortex-M3

Brand: NXP Semiconductors | Category: Controller | Size: 3 MB

: Lpc13Xx Memory Mapping

9
- Chapter 1: Lpc13Xx Introductory Information
  
  3
  - Introduction
    3
  - How to Read this Manual
    3
  - Features
    3
- Chapter 23 : Lpc13Xx Supplementary Information
  
  5
  - Ordering Options
    5
  - Block Diagram
    7
- Chapter 2: Lpc13Xx Memory Mapping
  
  8
  - How to Read this Chapter
    8
  - Memory Map
    8
    
    Table of Contents
    9
  - Memory Remapping
    9
- Chapter 3: Lpc13Xx System Configuration
  
  10
  - How to Read this Chapter
    10
    
    BOD Control
    10
    
    Reserved
    10
    
    Ssp1
    10
    
    USB Clocking and Power Control
    10
    
    Enabling Sequence for UART Clock
    11
    
    Entering Deep Power-Down Mode
    11
    
    Input Pins to the Start Logic
    11
    
    PIO Reset Status Registers
    11
  - Introduction
    11
    
    Reserved
    11
  - Pin Description
    12
    
    Reserved
    12
  - Clocking and Power Control
    13
    
    Reserved
    13
  - Register Description
    14
    
    Reserved
    14
    
    Reserved
    15
  - System Memory Remap Register
    16
    
    Reserved
    16
  - Peripheral Reset Control Register
    17
  - System PLL Control Register
    17
    
    Reserved
    17
  - System PLL Status Register
    18
  - USB PLL Control Register
    18
    
    Reserved
    18
  - USB PLL Status Register
    19
    
    Reserved
    19
  - System Oscillator Control Register
    20
  - Watchdog Oscillator Control Register
    20
    
    Reserved
    20
  - Internal Resonant Crystal Control Register
    21
    
    Reserved
    21
  - System PLL Clock Source Select Register
    22
    
    Reserved
    22
  - System Reset Status Register
    22
  - System PLL Clock Source Update Enable Register
    23
  - USB PLL Clock Source Select Register
    23
    
    Reserved
    23
  - Main Clock Source Select Register
    24
  - Main Clock Source Update Enable Register
    24
    
    Reserved
    24
  - USB PLL Clock Source Update Enable Register
    24
  - System AHB Clock Control Register
    25
    
    Reserved
    25
    
    Reserved
    26
  - System AHB Clock Divider Register
    25
  - SSP0 Clock Divider Register
    27
  - UART Clock Divider Register
    27
    
    Reserved
    27
  - SSP1 Clock Divider Register
    28
  - SYSTICK Clock Divider Register
    28
  - Trace Clock Divider Register
    28
  - USB Clock Source Select Register
    28
    
    Reserved
    28
  - USB Clock Divider Register
    29
    
    Reserved
    29
  - USB Clock Source Update Enable Register
    29
  - WDT Clock Divider Register
    30
    
    Reserved
    30
  - WDT Clock Source Select Register
    30
  - WDT Clock Source Update Enable Register
    30
  - CLKOUT Clock Divider Register
    31
    
    Reserved
    31
  - CLKOUT Clock Source Select Register
    31
  - CLKOUT Clock Source Update Enable Register
    31
  - POR Captured PIO Status Register 0
    32
  - POR Captured PIO Status Register 1
    32
    
    Reserved
    32
  - BOD Control Register
    33
  - System Tick Counter Calibration Register
    33
    
    Reserved
    33
  - Start Logic Edge Control Register 0
    34
  - Start Logic Signal Enable Register 0
    34
    
    Reserved
    34
  - Start Logic Edge Control Register 1
    35
    
    Reserved
    35
  - Start Logic Reset Register 0
    35
  - Start Logic Status Register 0
    35
  - Start Logic Reset Register 1
    36
    
    Reserved
    36
  - Start Logic Signal Enable Register 1
    36
  - Deep-Sleep Mode Configuration Register
    37
    
    Reserved
    37
  - Start Logic Status Register 1
    37
  - Wake-Up Configuration Register
    38
    
    Reserved
    38
  - Power-Down Configuration Register
    39
    
    Reserved
    39
    
    Reserved
    40
  - Device ID Register
    41
  - Reset
    41
  - Start-Up Behavior
    41
    
    Reserved
    41
  - Brown-Out Detection
    42
  - Power Management
    42
    
    Reserved
    42
  - Active Mode
    43
  - Power Configuration in Active Mode
    43
  - Power Configuration in Sleep Mode
    43
  - Programming Sleep Mode
    43
    
    Reserved
    43
  - Sleep Mode
    43
  - Deep-Sleep Mode
    44
  - Power Configuration in Deep-Sleep Mode
    44
  - Programming Deep-Sleep Mode
    44
    
    Reserved
    44
  - Wake-Up from Sleep Mode
    44
  - Deep Power-Down Mode
    45
  - Power Configuration in Deep Power-Down Mode
    45
    
    Reserved
    45
  - Wake-Up from Deep-Sleep Mode
    45
  - Deep-Sleep Mode Details
    46
  - IRC Oscillator
    46
    
    Reserved
    46
  - Programming Deep Power-Down Mode
    46
  - Wake-Up from Deep Power-Down Mode
    46
  - PLL (System PLL and USB PLL) Functional Description
    47
  - Start Logic
    47
  - Using the General Purpose Counter/Timers to Create a Self-Wake-Up Event
    47
  - Lock Detector
    48
    
    Reserved
    48
  - Divider Ratio Programming
    49
    
    Changing the Divider Values
    49
    
    Feedback Divider
    49
    
    Post Divider
    49
  - Frequency Selection
    49
    
    Reserved
    49
  - Power-Down Control
    49
  - Normal Mode
    50
  - Power-Down Mode
    50
    
    Reserved
    50
  - Flash Memory Access
    51
    
    Reserved
    51
- Chapter 4: Lpc13Xx Power Management Unit (PMU)
  
  52
  - Introduction
    52
  - Power Control Register
    52
    
    Reserved
    52
  - Register Description
    52
  - Functional Description
    53
    
    Reserved
    53
  - General Purpose Register 4
    53
  - General Purpose Registers 0 to 3
    53
- Chapter 5: Lpc13Xx Power Profiles
  
  54
  - Description
    54
    
    Reserved
    54
  - Features
    54
  - How to Read this Chapter
    54
  - Clocking Routine
    55
  - Definitions
    55
  - Set_Pll
    55
    
    Reserved
    55
  - Param0: System PLL Input Frequency and Param1: Expected System Clock
    56
  - Param2: Mode
    56
    
    Reserved
    56
  - Code Examples
    57
  - Invalid Frequency
    57
    
    Exceeded)
    57
  - Invalid Frequency Selection
    57
    
    Reserved
    57
    
    Restrictions)
    57
  - Param3: System PLL Lock Time-Out
    57
  - Exact Solution Cannot be Found (PLL)
    58
  - System Clock Approximately Equal to the Expected
    58
    
    Reserved
    58
  - System Clock Greater than or Equal to the Expected Value
    58
  - System Clock Less than or Equal to the Expected
    58
    
    Value
    58
  - Power Routine
    59
  - Set_Power
    59
    
    Reserved
    59
  - Param0: Main Clock
    60
  - Param1: Mode
    60
  - Param2: System Clock
    60
    
    Reserved
    60
  - An Applicable Power Setup
    61
    
    Reserved
    61
- Chapter 6 : Lpc13Xx Interrupt Controller
  
  62
  - Code Examples
    61
  - Invalid Frequency
    61
    
    Exceeded)
    61
  - Features
    62
  - How to Read this Chapter
    62
  - Interrupt Sources
    62
    
    Reserved
    62
    
    Reserved
    63
  - Introduction
    62
  - Vector Table Remapping
    64
    
    Example
    64
    
    Reserved
    64
  - Register Description
    65
    
    Xe000
    65
    
    Interrupt Set-Enable Register 0 Register
    66
    
    Reserved
    66
    
    Interrupt Set-Enable Register 1
    67
    
    Reserved
    67
  - Interrupt Clear-Enable Register 0
    68
    
    Reserved
    68
  - Interrupt Clear-Enable Register 1 Register
    69
    
    Reserved
    69
  - Interrupt Set-Pending Register 0 Register
    70
    
    Reserved
    70
  - Interrupt Set-Pending Register 1 Register
    71
    
    Reserved
    71
    
    Reserved
    72
    
    Reserved
    73
    
    Reserved
    74
  - Interrupt Clear-Pending Register 0 Register 72
    75
    
    Reserved
    75
  - Interrupt Active Bit Register 1
    76
    
    Reserved
    76
  - Interrupt Priority Register 0
    77
  - Interrupt Priority Register 1
    77
    
    Reserved
    77
  - Interrupt Priority Register 2
    78
  - Interrupt Priority Register 3
    78
    
    Reserved
    78
  - Interrupt Priority Register 4
    79
  - Interrupt Priority Register 5
    79
    
    Reserved
    79
  - Interrupt Priority Register 6
    80
  - Interrupt Priority Register 7
    80
    
    Reserved
    80
  - Interrupt Priority Register 8
    81
  - Interrupt Priority Register 9
    81
    
    Reserved
    81
  - Interrupt Priority Register 10
    82
  - Interrupt Priority Register 11
    82
    
    Reserved
    82
  - Interrupt Priority Register 12
    83
  - Interrupt Priority Register 13
    83
    
    Reserved
    83
  - Interrupt Priority Register 14
    84
  - Software Trigger Interrupt Register
    84
    
    Reserved
    84
- Chapter 7 : Lpc13Xx I/O Configuration
  
  85
  - How to Read this Chapter
    85
  - Introduction
    85
  - General Description
    86
  - Pin Function
    86
  - Pin Mode
    86
    
    Reserved
    86
  - A/D-Mode
    87
  - Hysteresis
    87
  - I 2 C Mode
    87
  - Open-Drain Mode
    87
  - Register Description
    87
    
    Reserved
    87
    
    Reserved
    88
    
    Reserved
    89
  - Iocon_Pio2_6
    90
    
    Reserved
    90
  - Iocon_Pio2_0
    91
    
    Reserved
    91
  - Iocon_Nreset_Pio0_0
    92
  - Iocon_Pio0_1
    92
    
    Reserved
    92
  - Iocon_Pio0_2
    93
    
    Reserved
    93
  - Iocon_Pio1_8
    93
  - Iocon_Pio2_7
    94
  - Iocon_Pio2_8
    94
    
    Reserved
    94
  - Iocon_Pio2_1
    95
    
    Reserved
    95
  - Iocon_Pio0_3
    96
  - Iocon_Pio0_4
    96
    
    Reserved
    96
  - Iocon_Pio0_5
    97
  - Iocon_Pio1_9
    97
    
    Reserved
    97
  - Iocon_Pio2_4
    98
    
    Reserved
    98
  - Iocon_Pio3_4
    98
  - Iocon_Pio2_5
    99
  - Iocon_Pio3_5
    99
    
    Reserved
    99
  - Iocon_Pio0_6
    100
  - Iocon_Pio0_7
    100
    
    Reserved
    100
  - Iocon_Pio2_10
    101
    
    Reserved
    101
  - Iocon_Pio2_9
    101
  - Iocon_Pio0_8
    102
    
    Reserved
    102
  - Iocon_Pio2_2
    102
  - Iocon_Pio0_9
    103
    
    Reserved
    103
  - Iocon_Pio1_10
    104
    
    Reserved
    104
  - Iocon_Swclk_Pioo_10
    104
  - Iocon_Pio2_11
    105
    
    Reserved
    105
  - Iocon_R_Pio0_11
    106
  - Iocon_R_Pio1_0
    106
    
    Reserved
    106
  - Iocon_R_Pio1_1
    107
    
    Reserved
    107
  - Iocon_R_Pio1_2
    108
    
    Reserved
    108
  - Iocon_Pio3_0
    109
  - Iocon_Pio3_1
    109
    
    Reserved
    109
  - Iocon_Pio2_3
    110
  - Iocon_Swdio_Pio1_3
    110
    
    Reserved
    110
  - Iocon_Pio1_4
    111
    
    Reserved
    111
  - Iocon_Pio1_11
    112
    
    Reserved
    112
  - Iocon_Pio1_5
    113
    
    Reserved
    113
  - Iocon_Pio3_2
    113
  - Iocon_Pio1_6
    114
  - Iocon_Pio1_7
    114
    
    Reserved
    114
  - Iocon_Pio_3_3
    115
    
    Reserved
    115
  - Iocon_Dcd_Loc
    116
    
    Reserved
    116
  - Iocon_Dsr_Loc
    116
  - Iocon_Sck0_Loc
    116
  - Iocon_Ri_Loc
    117
    
    Reserved
    117
- Chapter 8: Lpc13Xx Pin Configuration
  
  118
  - How to Read this Chapter
    118
    
    Reserved
    118
  - Lpc134X Pin Configuration
    119
    
    Reserved
    119
    
    Reserved
    120
  - Lpc131X Pin Configuration
    121
    
    Reserved
    121
  - Pin Description
    122
    
    Reserved
    122
  - LQFP48 Packages
    123
    
    Reserved
    123
    
    Reserved
    124
    
    Reserved
    125
    
    Reserved
    126
  - HVQFN33 Packages
    127
    
    Reserved
    127
    
    Reserved
    128
    
    Reserved
    129
  - Features
    130
  - How to Read this Chapter
    130
  - Pin Description
    130
    
    Reserved
    130
- Chapter 9: Lpc13Xx General Purpose I/O (GPIO)
  
  131
  - GPIO Data Register
    131
    
    X5000
    131
  - Register Description
    131
  - GPIO Data Direction Register
    132
  - GPIO Interrupt Sense Register
    132
    
    Reserved
    132
  - GPIO Interrupt both Edges Sense Register
    133
  - GPIO Interrupt Event Register
    133
  - GPIO Interrupt Mask Register
    133
  - GPIO Raw Interrupt Status Register
    133
    
    Reserved
    133
  - GPIO Interrupt Clear Register
    134
    
    Reserved
    134
  - GPIO Masked Interrupt Status Register
    134
  - Functional Description
    135
  - Write/Read Data Operations
    135
    
    Read Operation
    135
    
    Reserved
    135
    
    Write Operation
    135
  - Basic Configuration
    136
- Chapter 10: Lpc13Xx USB Device Controller
  
  136
  - How to Read this Chapter
    136
  - Introduction
    136
    
    Reserved
    136
  - Features
    137
  - Fixed Endpoint Configuration
    137
    
    Reserved
    137
  - Analog Transceiver
    138
  - Endpoint RAM (EP_RAM)
    138
  - EP_RAM Access Control
    138
    
    Reserved
    138
  - General Description
    138
  - Serial Interface Engine (SIE)
    138
  - Operational Overview
    139
    
    Reserved
    139
  - Register Interface
    139
  - Softconnect
    139
  - Clocking and Power Control
    140
  - Clocks
    140
    
    Reserved
    140
  - Pin Description
    140
  - Power Requirements
    140
  - Power Management Support
    141
    
    Reserved
    141
  - Interrupts
    142
  - Register Description
    142
    
    Reserved
    142
  - Remote Wake-Up
    142
  - Device Interrupt Registers
    143
  - USB Device Interrupt Status Register (Usbdevintst - 0X4002 0000)
    143
  - USB Device Interrupt Enable Register (Usbdevinten - 0X4002 0004)
    144
    
    Reserved
    144
    
    Reserved
    145
  - USB Device Interrupt Clear Register (Usbdevintclr - 0X4002 0008)
    146
    
    Reserved
    146
  - USB Device Interrupt Set Register
    147
    
    0X4002 000C)
    147
    
    Reserved
    147
    
    Reserved
    148
  - SIE Command Code Registers
    149
  - USB Command Code Register
    149
    
    0X4001 8010)
    149
    
    Reserved
    149
  - USB Command Data Register
    150
    
    0X4002 0014)
    150
  - USB Data Transfer Registers
    150
  - USB Receive Data Register
    150
  - USB Receive Packet Length Register (Usbrxplen - 0X4002 0020)
    150
    
    Reserved
    150
  - USB Transmit Data Register
    150
    
    150
    150
  - USB Control Register
    151
    
    0X4002 0028)
    151
    
    Reserved
    151
  - USB Transmit Packet Length Register (Usbtxplen - 0X4002 0024)
    151
  - Data Transfer
    152
    
    Reserved
    152
  - Miscellaneous Registers
    153
  - Serial Interface Engine Command Description
    153
    
    Reserved
    153
    
    Reserved
    154
  - USB Device FIQ Select Register
    153
    
    0X4002 002C)
    153
  - Configure Device (Command: 0Xd8, Data: Write 1 Byte)
    155
    
    Reserved
    155
  - Set Address (Command: 0Xd0, Data: Write 1 Byte)
    155
  - Read Interrupt Status (Command: 0Xf4, Data: Read 2 Bytes)
    156
    
    Reserved
    156
  - Set Mode (Command: 0Xf3, Data: Write 1 Byte)
    156
  - Read Chip ID (Command: 0Xfd, Data: Read 2 Bytes)
    157
    
    Reserved
    157
    
    Set Device Status (Command: 0Xfe, Data: Write 1 Byte)
    157
  - Read Current Frame Number (Command: 0Xf5, Data: Read 1 or 2 Bytes)
    157
  - Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
    158
    
    Reserved
    158
  - Get Error Code (Command: 0Xff, Data: Read 1 Byte)
    159
  - Select Endpoint (Command: 0X00 - 0X09 Data: Read 1 Byte (Optional))
    159
  - Select Endpoint/Clear Interrupt (Command: 0X40 - 0X47, Data: Read 1 Byte)
    160
    
    Reserved
    160
  - Set Endpoint Status (Command: 0X40 - 0X49, Data: Write 1 Byte (Optional))
    161
    
    (Optional))
    161
    
    None)
    162
    
    USB Device Controller Initialization
    162
  - USB Clock Configuration
    162
    
    Reserved
    162
  - Data Flow from the Host to the Device
    163
    
    Reserved
    163
  - Functional Description
    163
  - USB Device Controller Initialization
    163
  - Data Flow from the Device to the Host
    164
  - Interrupt Based Transfer
    164
  - Isochronous Transfer
    164
    
    Reserved
    164
  - Automatic Stall Feature
    165
  - Bulk Endpoints
    165
    
    Reserved
    165
    
    Reserved
    166
  - Double-Buffered Endpoint Operation
    165
  - Isochronous Endpoints
    167
    
    Reserved
    167
- Chapter 11: Lpc13Xx USB On-Chip Drivers
  
  168
  - Clock and Pin Initialization
    168
    
    Reserved
    168
  - How to Read this Chapter
    168
  - Introduction
    168
  - USB Driver Functions
    168
  - Calling the USB Device Driver
    169
    
    X1Fff
    169
  - USB Connect
    169
  - USB Initialization
    169
  - USB Interrupt Handler
    169
  - USB Mass Storage Driver
    170
    
    Reserved
    170
  - USB Human Interface Driver
    171
    
    Reserved
    171
  - ROM Driver Table
    172
  - USB Device Information
    172
    
    Reserved
    172
  - USB Driver Structure Definitions
    172
  - USB Driver Table
    172
  - Mass Storage Device Information
    173
    
    Reserved
    173
  - Human Interface Device Information
    174
    
    Reserved
    174
  - Standard Descriptor
    175
    
    Reserved
    175
  - USB Descriptors
    175
  - HID Configuration, Interface, Class, Endpoint, and Report Descriptor
    176
    
    Reserved
    176
    
    Reserved
    177
  - Mass Storage Configuration, Interface, and Endpoint Descriptors
    176
  - Example Descriptors
    178
    
    Example HID Descriptor
    178
    
    Reserved
    178
    
    Example MSC Descriptor
    179
    
    Reserved
    179
- Chapter 12 : Lpc13Xx UART
  
  180
  - Basic Configuration
    180
  - Features
    180
  - How to Read this Chapter
    180
  - Pin Description
    180
    
    Reserved
    180
  - Clocking and Power Control
    181
  - Register Description
    181
    
    Reserved
    181
    
    X0000
    182
  - UART Divisor Latch LSB and MSB Registers (U0DLL - 0X4000 8000 and U0DLM - 0X4000 8004, When DLAB = 1)
    183
    
    Reserved
    183
  - UART Receiver Buffer Register
    183
    
    0X4000 8000, When DLAB = 0, Read Only)
    183
  - UART Transmitter Holding Register (U0THR - 12.6.15 0X4000 8000 When DLAB = 0, Write Only)
    183
  - UART Interrupt Enable Register (U0IER - 0X4000 8004, When DLAB = 0)
    184
    
    X4005
    184
  - UART Interrupt Identification Register (U0IIR - 0X4004 8008, Read Only)
    185
    
    Reserved
    185
    
    Reserved
    186
  - UART FIFO Control Register (U0FCR - 0X4000 8008, Write Only)
    187
    
    Reserved
    187
  - UART Line Control Register (U0LCR - 0X4000 800C)
    188
    
    Reserved
    188
  - UART Modem Control Register
    189
    
    Reserved
    189
  - Auto-Flow Control
    190
  - Auto-RTS
    190
    
    Reserved
    190
  - Auto-CTS
    191
    
    Reserved
    191
  - UART Line Status Register (U0LSR - 0X4000 8014, Read Only)
    192
    
    Reserved
    192
    
    Reserved
    193
  - UART Modem Status Register
    194
  - UART Scratch Pad Register (U0SCR - 0X4000 801C)
    194
    
    Reserved
    194
  - UART Auto-Baud Control Register (U0ACR - 0X4000 8020)
    195
    
    Auto-Baud
    195
    
    Reserved
    195
  - Auto-Baud Modes
    196
    
    Reserved
    196
    
    Reserved
    197
    
    Reserved
    198
    
    UART Fractional Divider Register (U0FDR - 0X4000 8028)
    198
  - Baud Rate Calculation
    199
    
    Reserved
    199
    
    Reserved
    200
  - UART Transmit Enable Register (U0TER - 0X4000 8030)
    201
    
    Reserved
    201
  - UART RS485 Control Register (U0RS485CTRL - 0X4000 804C)
    202
    
    Reserved
    202
  - RS-485/EIA-485 Modes of Operation
    203
    
    Reserved
    203
    
    Reserved
    204
    
    RS-485/EIA-485 Auto Address Detection (AAD) Mode
    204
    
    RS-485/EIA-485 Auto Direction Control
    204
    
    RS-485/EIA-485 Normal Multidrop Mode (NMM)
    204
    
    RS485/EIA-485 Driver Delay Time
    205
    
    RS485/EIA-485 Output Inversion
    205
  - UART RS485 Address Match Register
    203
  - UART1 RS485 Delay Value Register
    203
  - Architecture
    205
    
    Reserved
    205
    
    Reserved
    206
  - Applications
    207
  - Basic Configuration
    207
- Chapter 13: Lpc13Xx I2C-Bus Controller
  
  207
  - Features
    207
  - General Description
    207
    
    Reserved
    207
  - How to Read this Chapter
    207
  - C Fast-Mode Plus
    208
    
    Reserved
    208
  - Clocking and Power Control
    209
  - Pin Description
    209
  - Register Description
    209
    
    X0000
    209
  - C Control Set Register (I2C0CONSET - 0X4000 0000)
    210
    
    Reserved
    210
    
    Reserved
    211
  - C Data Register (I2C0DAT - 0X4000 0008)
    212
  - C Slave Address Register 0 (I2C0ADR0- 0X4000 000C)
    212
    
    Reserved
    212
  - C Status Register (I2C0STAT - 0X4000 0004)
    212
  - C SCL HIGH and LOW Duty Cycle Registers (I2C0SCLH - 0X4000 0010 and I2C0SCLL- 0X4000 0014)
    213
  - Selecting the Appropriate I C Data Rate and Duty Cycle
    213
    
    Reserved
    213
  - C Control Clear Register (I2C0CONCLR - 0X4000 0018)
    214
  - C Monitor Mode Control Register (I2C0MMCTRL - 0X4000 001C)
    214
    
    Reserved
    214
  - Interrupt in Monitor Mode
    215
    
    Reserved
    215
  - Loss of Arbitration in Monitor Mode
    216
    
    0X4000 002C)
    216
    
    I 2 C Slave Address Registers (I2C0ADR[1, 2, 3]- 0X4000 00[20, 24, 28])
    216
    
    Reserved
    216
  - C Operating Modes
    217
  - I 2 C Mask Registers (I2C0MASK[0, 1, 2, 3] - 0X4000 00[30, 34, 38, 3C])
    217
  - Master Transmitter Mode
    217
    
    Reserved
    217
  - Master Receiver Mode
    218
    
    Reserved
    218
  - Slave Receiver Mode
    219
    
    Reserved
    219
  - C Implementation and Operation
    220
    
    Reserved
    220
  - Slave Transmitter Mode
    220
  - Input Filters and Output Stages
    221
    
    Reserved
    221
  - Address Mask Registers, I2MASK0 to I2MASK3
    222
  - Address Registers, I2ADDR0 to I2ADDR3
    222
  - Arbitration and Synchronization Logic
    222
    
    Reserved
    222
  - Comparator
    222
  - Shift Register, I2DAT
    222
  - Serial Clock Generator
    223
    
    Reserved
    223
  - Control Register, I2CONSET and I2CONCLR
    224
  - Details of I C Operating Modes
    224
    
    Reserved
    224
  - Status Decoder and Status Register
    224
  - Timing and Control
    224
  - Master Transmitter Mode
    225
    
    Reserved
    225
    
    Reserved
    226
    
    Reserved
    227
    
    Reserved
    228
  - Master Receiver Mode
    229
  - NXP B.V. 2011. All Rights Reserved
    229
    
    Reserved
    230
    
    Reserved
    231
  - Slave Receiver Mode
    232
    
    Reserved
    232
    
    Reserved
    233
    
    Reserved
    234
    
    Reserved
    235
  - Slave Transmitter Mode
    236
    
    Reserved
    236
    
    Reserved
    237
  - I2STAT = 0X00
    238
    
    Reserved
    238
  - I2STAT = 0Xf8
    238
  - Miscellaneous States
    238
  - Simultaneous Repeated START Conditions from
    239
    
    Reserved
    239
    
    Two Masters
    239
  - Some Special Cases
    239
  - Data Transfer after Loss of Arbitration
    240
  - Forced Access to the I C-Bus
    240
    
    Reserved
    240
  - Bus Error
    241
  - C State Service Routines
    241
    
    Reserved
    241
  - C-Bus Obstructed by a LOW Level on SCL or SDA
    241
  - Adapting State Services to an Application
    242
  - C Interrupt Service
    242
  - Initialization
    242
  - Initialization Routine
    242
  - Software Example
    242
  - Start Master Transmit Function
    242
    
    Reserved
    242
  - The State Service Routines
    242
  - I 2 C Interrupt Routine
    243
  - Master States
    243
  - Non Mode Specific States
    243
  - Start Master Receive Function
    243
  - State: 0X00
    243
  - State: 0X08
    243
    
    Reserved
    243
  - Master Transmitter States
    244
  - State: 0X10
    244
  - State: 0X18
    244
  - State: 0X20
    244
  - State: 0X28
    244
    
    Reserved
    244
  - Master Receive States
    245
  - State: 0X30
    245
  - State: 0X38
    245
  - State: 0X40
    245
  - State: 0X48
    245
  - State: 0X50
    245
    
    Reserved
    245
  - Slave Receiver States
    246
  - State: 0X58
    246
  - State: 0X60
    246
  - State: 0X68
    246
  - State: 0X70
    246
    
    Reserved
    246
  - State: 0X78
    247
  - State: 0X80
    247
  - State: 0X88
    247
  - State: 0X90
    247
    
    Reserved
    247
  - Slave Transmitter States
    248
  - State: 0X98
    248
  - State: 0Xa0
    248
  - State: 0Xa8
    248
  - State: 0Xb0
    248
  - State: 0Xb8
    248
    
    Reserved
    248
  - State: 0Xc0
    249
  - State: 0Xc8
    249
    
    Reserved
    249
  - Basic Configuration
    250
- Chapter 14: Lpc13Xx SSP0/1
  
  250
  - Features
    250
  - General Description
    250
    
    Reserved
    250
  - How to Read this Chapter
    250
  - Pin Description
    251
    
    Reserved
    251
  - Clocking and Power Control
    252
  - Register Description
    252
    
    Reserved
    252
    
    Reserved
    253
  - SSP Control Register 0
    254
  - SSP Control Register 1
    254
    
    Reserved
    254
  - SSP Data Register
    255
    
    Reserved
    255
  - SSP Clock Prescale Register
    256
  - SSP Interrupt Mask Set/Clear Register
    256
    
    Reserved
    256
  - SSP Status Register
    256
  - SSP Masked Interrupt Status Register
    257
    
    Reserved
    257
  - SSP Raw Interrupt Status Register
    257
  - Functional Description
    258
  - SSP Interrupt Clear Register
    258
  - Texas Instruments Synchronous Serial Frame Format
    258
    
    Reserved
    258
  - SPI Frame Format
    259
    
    Reserved
    259
  - Clock Polarity (CPOL) and Phase (CPHA) Control 259 14.8.2.2 SPI Format with CPOL=0,CPHA=0
    260
    
    Reserved
    260
  - SPI Format with CPOL = 1,CPHA = 0
    261
    
    Reserved
    261
    
    Reserved
    262
  - SPI Format with CPOL=0,CPHA=1
    261
  - Semiconductor Microwire Frame Format
    263
    
    Reserved
    263
    
    Reserved
    264
  - SPI Format with CPOL = 1,CPHA = 1
    263
  - Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
    265
    
    Reserved
    265
- Chapter 15 : Lpc13Xx 16-Bit Timer/Counters (CT16B0/1)
  
  266
  - Applications
    266
    
    Reserved
    266
  - Basic Configuration
    266
  - Features
    266
  - How to Read this Chapter
    266
  - Clocking and Power Control
    267
  - Description
    267
  - Pin Description
    267
  - Register Description
    267
    
    Reserved
    267
    
    Reserved
    268
  - Interrupt Register (TMR16B0IR and TMR16B1IR)
    269
    
    Reserved
    269
  - Prescale Register (TMR16B0PR - Address 0X4000 C00C and TMR16B1PR - Address 0X4001 000C)
    270
    
    Reserved
    270
  - Timer Control Register (TMR16B0TCR and TMR16B1TCR)
    270
  - Timer Counter (TMR16B0TC - Address 0X4000 C008 and TMR16B1TC - Address 0X4001 0008)
    270
  - Match Control Register (TMR16B0MCR and TMR16B1MCR)
    271
    
    Reserved
    271
  - Prescale Counter Register (TMR16B0PC - Address 0X4000 C010 and TMR16B1PC - Address 0X4001 0010)
    271
  - Match Registers (TMR16B0MR0/1/2/3 - Addresses 0X4000 C018/1C/20/24 and TMR16B1MR0/1/2/3 - Addresses 0X4001 0018/1C/20/24)
    272
    
    Reserved
    272
  - Capture Control Register (TMR16B0CCR and TMR16B1CCR)
    273
  - Capture Register (CT16B0CR0 - Address 0X4000 C02C and CT16B1CR0 - Address 0X4001 002C)
    273
    
    Reserved
    273
  - External Match Register (TMR16B0EMR and TMR16B1EMR)
    274
    
    Reserved
    274
  - Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
    275
    
    Reserved
    275
  - PWM Control Register (TMR16B0PWMC and TMR16B1PWMC)
    276
    
    Reserved
    276
  - Rules for Single Edge Controlled PWM Outputs
    277
    
    Reserved
    277
  - Example Timer Operation
    278
    
    Reserved
    278
  - Architecture
    279
    
    Reserved
    279
  - Applications
    280
    
    Reserved
    280
  - Basic Configuration
    280
- Chapter 16: Lpc13Xx 32-Bit Timer/Counters (CT32B0/1)
  
  280
  - Features
    280
  - How to Read this Chapter
    280
  - Clocking and Power Control
    281
  - Description
    281
  - Pin Description
    281
  - Register Description
    281
    
    Reserved
    281
    
    Reserved
    282
  - Interrupt Register (TMR32B0IR and TMR32B1IR)
    283
    
    Reserved
    283
  - Prescale Register (TMR32B0PR - Address 0X4001 400C and TMR32B1PR - Address 0X4001 800C)
    284
    
    Reserved
    284
  - Timer Control Register (TMR32B0TCR and TMR32B1TCR)
    284
  - Timer Counter (TMR32B0TC - Address 0X4001 4008 and TMR32B1TC - Address 0X4001 8008)
    284
  - Match Control Register (TMR32B0MCR and TMR32B1MCR)
    285
    
    Reserved
    285
  - Prescale Counter Register (TMR32B0PC - Address 0X4001 4010 and TMR32B1PC - Address 0X4001 8010)
    285
  - Match Registers (TMR32B0MR0/1/2/3 - Addresses 0X4001 4018/1C/20/24 and TMR32B1MR0/1/2/3 Addresses 0X4001 8018/1C/20/24)
    286
    
    Reserved
    286
  - Capture Control Register (TMR32B0CCR and TMR32B1CCR)
    287
  - Capture Register (TMR32B0CR0 - Address 0X4001 402C and TMR32B1CR0 - Address 0X4001 802C)
    287
  - External Match Register (TMR32B0EMR and TMR32B1EMR)
    287
    
    Reserved
    287
    
    Reserved
    288
  - Count Control Register (TMR32B0CTCR and TMR32B1TCR)
    289
    
    Reserved
    289
  - PWM Control Register (TMR32B0PWMC and TMR32B1PWMC)
    290
    
    Reserved
    290
  - Rules for Single Edge Controlled PWM Outputs
    291
    
    Reserved
    291
  - Example Timer Operation
    292
    
    Reserved
    292
  - Architecture
    293
    
    Reserved
    293
  - Basic Configuration
    294
- Chapter 17: Lpc13Xx System Tick Timer
  
  294
  - Description
    294
    
    Reserved
    294
  - Features
    294
  - How to Read this Chapter
    294
  - Operation
    295
  - Register Description
    295
    
    Reserved
    295
  - System Timer Control and Status Register (CTRL - 0Xe000 E010)
    296
  - System Timer Current Value Register
    296
    
    0Xe000 E018)
    296
    
    Reserved
    296
  - System Timer Reload Value Register (LOAD - 0Xe000 E014)
    296
  - System Timer Calibration Value Register
    297
    
    0Xe000 E01C)
    297
    
    Reserved
    297
  - Example Timer Calculations
    298
    
    Reserved
    298
    
    System Clock = 12 Mhz
    298
    
    System Clock = 72 Mhz
    298
    
    System Tick Timer Clock = 24 Mhz
    298
- Chapter 18 : Lpc13Xx Watchdog Timer (WDT)
  
  299
  - Applications
    299
    
    Reserved
    299
  - Basic Configuration
    299
  - Features
    299
  - How to Read this Chapter
    299
  - Clocking and Power Control
    300
    
    Reserved
    300
  - Description
    300
  - Register Description
    301
  - Watchdog Mode Register (WDMOD - 0X4000 0000)
    301
    
    Reserved
    301
  - Watchdog Feed Register (WDFEED - 0X4000 4008)
    302
    
    Reserved
    302
  - Watchdog Timer Constant Register (WDTC - 0X4000 4004)
    302
  - Block Diagram
    303
    
    Reserved
    303
  - Watchdog Timer Value Register (WDTV - 0X4000 400C)
    303
  - Basic Configuration
    304
- Chapter 19: Lpc13Xx Windowed Watchdog Timer (WWDT)
  
  304
  - Features
    304
    
    Reserved
    304
  - How to Read this Chapter
    304
  - Applications
    305
  - General Description
    305
    
    Reserved
    305
  - Clocking and Power Control
    306
    
    Reserved
    306
  - Register Description
    307
  - Watchdog Mode Register
    307
    
    Reserved
    307
  - Watchdog Timer Constant Register
    308
    
    Reserved
    308
  - Watchdog Feed Register
    309
  - Watchdog Timer Value Register
    309
    
    Reserved
    309
  - Watchdog Timer Warning Interrupt Register 309 Watchdog Timer Window Register
    310
  - Watchdog Timing Examples
    310
    
    Reserved
    310
    
    Reserved
    311
  - Basic Configuration
    312
- Chapter 20: Lpc13Xx Analog-To-Digital Converter (ADC)
  
  312
  - Features
    312
  - How to Read this Chapter
    312
  - Pin Description
    312
    
    Reserved
    312
  - Clocking and Power Control
    313
  - Register Description
    313
    
    Reserved
    313
  - A/D Control Register (AD0CR - 0X4001 C000)
    314
    
    Reserved
    314
  - A/D Global Data Register (AD0GDR - 0X4001 C004)
    315
    
    Reserved
    315
  - A/D Data Registers (AD0DR0 to AD0DR7 - 0X4001 C010 to 0X4001 C02C)
    316
  - A/D Interrupt Enable Register (AD0INTEN - 0X4001 C00C)
    316
  - A/D Status Register (AD0STAT - 0X4001 C030)
    316
    
    Reserved
    316
  - Hardware-Triggered Conversion
    317
  - Interrupts
    317
    
    Reserved
    317
  - Operation
    317
  - Bootloader
    318
    
    Reserved
    318
- Chapter 21: Lpc13Xx Flash Memory Programming Firmware
  
  318
  - How to Read this Chapter
    318
  - Bootloader Code Version 5.2 Notes
    319
  - Description
    319
    
    Reserved
    319
  - Features
    319
  - Flash Content Protection Mechanism
    320
    
    Reserved
    320
  - Memory Map after any Reset
    320
  - Criterion for Valid User Code
    321
  - ISP Command Format
    321
  - ISP Response Format
    321
    
    Reserved
    321
  - ISP/IAP Communication Protocol
    321
  - Interrupts During IAP
    322
  - Interrupts During ISP
    322
  - ISP Command Abort
    322
  - ISP Data Format
    322
  - ISP Flow Control
    322
  - RAM Used by IAP Command Handler
    322
    
    Reserved
    322
  - RAM Used by ISP Command Handler
    322
  - Usage Note
    323
    
    Reserved
    323
  - USB Communication Protocol
    323
  - Boot Process Flowchart
    324
    
    Reserved
    324
  - Code Read Protection (CRP)
    325
    
    Reserved
    325
    
    Reserved
    326
  - Sector Numbers
    325
  - ISP Entry Protection
    327
    
    Reserved
    327
  - ISP Commands
    328
  - Unlock <Unlock Code
    328
    
    Reserved
    328
  - Echo <Setting
    329
  - Set Baud Rate <Baud Rate> <Stop Bit
    329
  - Write to RAM <Start Address> <Number of Bytes
    329
    
    Reserved
    329
  - Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number
    330
    
    Reserved
    330
  - Read Memory <Address> <No. of Bytes
    330
  - Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes
    331
    
    Reserved
    331
  - Go <Address> <Mode
    332
    
    Reserved
    332
  - Blank Check Sector(S) <Sector Number> <End Sector Number
    333
  - Erase Sector(S) <Start Sector Number> <End Sector Number
    333
  - Read Part Identification Number
    333
    
    Reserved
    333
    
    Return Code CMD_SUCCESS
    334
  - No of Bytes
    334
    
    Reserved
    334
  - Read Boot Code Version Number
    334
21.13.14 Readuid

335
- ISP Return Codes
  335
  - Reserved
    335
- Readuid
  335
- IAP Commands
  336
  - Reserved
    336
- Prepare Sector(S) for Write Operation
  337
  - Reserved
    337
  - Busy
    338
  - Cmd_Success
    338
  - Count_Error
    338
  - COUNT_ERROR (Byte Count Is Not 256 | 512 | 1024 | 4096) | SECTOR_NOT_PREPARED_FOR WRITE_OPERATION
    338
  - Dst_Addr_Error
    338
  - Dst_Addr_Not_Mapped
    338
  - Invalid_Sector
    338
  - Return Code CMD_SUCCESS
    338
  - Src_Addr_Error
    338
  - SRC_ADDR_ERROR (Address Not on Word Boundary) | DST_ADDR_ERROR (Address Not on Correct Boundary) | SRC_ADDR_NOT_MAPPED
    338
- Blank Check Sector(S)
  339
- Erase Sector(S)
  339
- Read Part Identification Number
  339
  - Reserved
    339
  - Addr_Error
    340
  - Addr_Not_Mapped
    340
  - Compare_Error
    340
  - Description
    340
- Compare <Address1> <Address2> <No of Bytes
  340
- Read Boot Code Version Number
  340
- Reinvoke ISP
  340
- Debug Notes
  341
- IAP Status Codes
  341
- Readuid
  341
- Flash Configuration Register
  342
  - Reserved
    342
- Register Description
  342
- Serial Wire Debug (SWD) Flash Programming Interface
  342
- Signature Generation Address and Control Registers
  343
  - Reserved
    343
- Flash Module Status Register
  344
  - Reserved
    344
- Signature Generation Result Registers
  344
- Algorithm and Procedure for Signature Generation
  345
  - Reserved
    345
  - Signature Generation
    345
  - Content Verification
    346
  - Reserved
    346
- Chapter 22 : Lpc13Xx Serial Wire Debug (SWD)
  
  347
  - Flash Module Status Clear Register
    345
  - Flash Signature Generation
    345
  - Description
    347
  - Features
    347
  - How to Read this Chapter
    347
  - Introduction
    347
  - Pin Description
    347
    
    Reserved
    347
  - Debug Connections
    348
    
    Reserved
    348
    
    Reserved
    349
  - Debug Limitations
    348
  - Debug Notes
    348
  - Abbreviations
    350
    
    Reserved
    350
  - Definitions
    351
  - Disclaimers
    351
  - Legal Information
    351
  - Trademarks
    351
    
    Reserved
    351
  - Tables
    352
    
    Reserved
    352
    
    Reserved
    353
    
    Reserved
    354
    
    Reserved
    355
    
    Reserved
    356
    
    Reserved
    357
    
    Reserved
    358
  - Figures
    359
    
    Reserved
    359
Contents/Reserved

360
- Contents
  360
  - Reserved
    360
  - Reserved
    361
  - Reserved
    362
  - Reserved
    363
  - Reserved
    364
  - Reserved
    365
  - Reserved
    366
  - Reserved
    367
  - Reserved
    368

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

More NXP Semiconductors Manuals

NXP Semiconductors LPC1313 Manuals

NXP Semiconductors LPC1313 User Manual (368 pages)

Table of Contents

: Lpc13Xx Memory Mapping

Chapter 1: Lpc13Xx Introductory Information

Chapter 23 : Lpc13Xx Supplementary Information

Chapter 2: Lpc13Xx Memory Mapping

Chapter 3: Lpc13Xx System Configuration

Chapter 4: Lpc13Xx Power Management Unit (PMU)

Chapter 5: Lpc13Xx Power Profiles

Chapter 6 : Lpc13Xx Interrupt Controller

Chapter 7 : Lpc13Xx I/O Configuration

Chapter 8: Lpc13Xx Pin Configuration

Chapter 9: Lpc13Xx General Purpose I/O (GPIO)

Chapter 10: Lpc13Xx USB Device Controller

Chapter 11: Lpc13Xx USB On-Chip Drivers

Chapter 12 : Lpc13Xx UART

Chapter 13: Lpc13Xx I2C-Bus Controller

Chapter 14: Lpc13Xx SSP0/1

Chapter 15 : Lpc13Xx 16-Bit Timer/Counters (CT16B0/1)

Chapter 16: Lpc13Xx 32-Bit Timer/Counters (CT32B0/1)

Chapter 17: Lpc13Xx System Tick Timer

Chapter 18 : Lpc13Xx Watchdog Timer (WDT)

Chapter 19: Lpc13Xx Windowed Watchdog Timer (WWDT)

Chapter 20: Lpc13Xx Analog-To-Digital Converter (ADC)

Chapter 21: Lpc13Xx Flash Memory Programming Firmware

21.13.14 Readuid

Chapter 22 : Lpc13Xx Serial Wire Debug (SWD)

Contents/Reserved

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