Freescale Semiconductor MPC8358E Hardware Specificftion page 91

CFG_CLKIN_DIV
1
at Reset
High
High
High
High
High
High
High
High
High
High
High
1
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in
agent mode.
2
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
22.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 73
in Table 73 should be considered reserved.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
Table 72. CSB Frequency Options (continued)
SPMF
Input Clock Ratio
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
shows the encodings for RCWL[COREPLL]. COREPLL values not listed
Table 73. e300 Core PLL Configuration
RCWL[COREPLL]
0–1 2–5 6
nn 0000 n
00 0001 0
01 0001 0
10 0001 0
11 0001 0
00 0001 1
01 0001 1
10 0001 1
csb_clk :
16.67
2
6:1
7:1
8:1
9:1
10:1
11:1
12:1
13:1
14:1
15:1
16:1
core_clk : csb_clk
Ratio
PLL bypassed
(PLL off, csb_clk
clocks core directly) clocks core directly)
1:1
1:1
1:1
1:1
1.5:1
1.5:1
1.5:1
Input Clock Frequency (MHz)
25 33.33
csb_clk Frequency (MHz)
200
233
VCO divider
PLL bypassed
(PLL off, csb_clk
÷
2
÷
4
÷
8
÷
8
÷
2
÷
4
÷
8
Clocking
2
66.67
91