Freescale Semiconductor MPC8358E Hardware Specificftion page 19

Table 12 provides the PLL and DLL lock times.
Parameter/Condition
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
5.3 QUICC Engine Block Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine
block's communication interfaces.
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QUICC Engine block
operating frequency setting for meeting the performance target. Because the
performance is a complex function of all the QUICC Engine block settings,
the user should make use of the QUICC Engine block performance utility
tool provided by Freescale to validate their system.
Table 13 lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block
core frequency for each interface.
Table 13. QUICC Engine Block Operating Frequency Limitations
Interface
Ethernet Management: MDC/MDIO
MII
RMII
GMII/RGMII/TBI/RTBI
SPI (master/slave)
UCC through TDM
MCC
UTOPIA L2
POS-PHY L2
HDLC bus
HDLC/transparent
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
Table 12. PLL and DLL Lock Times
NOTE
Interface Operating
Frequency (MHz)
10 (max)
25 (typ)
50 (typ)
125 (typ)
10 (max)
50 (max)
25 (max)
50 (max)
50 (max)
10 (max)
50 (max)
Min Max
— 100
7680 122,880
Section 22, "Clocking," for more information.
Min QUICC Engine
Max Interface Bit
Rate (Mbps)
Frequency
10
100
100
1000
10
70
16.67
800
800
10
50
RESET Initialization
Unit Notes
μs
—
csb_clk cycles 1, 2
Operating Notes
1
(MHz)
20 —
50 —
50 —
250 —
20 —
8 × F
2
16 × F
2, 4
2 × F
2
2 × F
2
20 —
8/3 × F
2, 3
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