Freescale Semiconductor MPC8358E Hardware Specificftion page 36

Powerquicc ii pro processor revision 2.x tbga silicon
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 33
provides the TBI transmit AC timing specifications.
At recommended operating conditions with LV
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to TBI data TCG[9:0] delay
GTX_CLK clock rise time, (20% to 80%)
GTX_CLK clock fall time, (80% to 20%)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
transmit timing (TT) with respect to the time from t
state (V) or setup time. Also, t
(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of t
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
TTX
letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
3. In rev. 2.0 silicon, due to errata, t
MPC8360E, Rev. 1 .
Figure 18
shows the TBI transmit AC timing diagram.
GTX_CLK
TXD[7:0]
TX_EN
TX_ER
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
36
Table 33. TBI Transmit AC Timing Specifications
/OV
of 3.3 V ± 10%.
DD
DD
Symbol
t
TTXH
t
t
t
G125H
(K) going high (H) until the referenced data signals (D) reach the valid
TTX
symbolizes the TBI transmit timing (TT) with respect to the time from t
TTKHDX
minimum is 0.7 ns for UCC1. Refer to Errata QE_ENET19 in Chip Errata for the
TTKHDX
t
TTX
t
TTXH
Figure 18. TBI Transmit AC Timing Diagram
1
Min
t
TTX
/t
40
TTX
1.0
TTKHDX
TTKHDV
t
TTXR
t
TTXF
t
G125
/t
45
G125
(first two letters of functional block)(signal)(state )(reference)(state)
for outputs. For example, t
t
TTXR
t
TTXF
t
TTKHDX
Typ
Max
Unit
8.0
ns
60
%
ns
5.0
1.0
ns
1.0
ns
8.0
ns
55
ns
symbolizes the TBI
TTKHDV
(K) going high
TTX
Freescale Semiconductor
Notes
3
2
for

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