Freescale Semiconductor MPC8358E Hardware Specificftion page 90

Clocking
The system VCO frequency is derived from the following equations:
• csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
• System VCO Frequency = csb_clk × VCO divider (if both RCWL[DDRCM] and RCWL[LBCM]
are cleared)
OR
System VCO frequency = 2 × csb_clk × VCO divider (if either RCWL[DDRCM] or
•
RCWL[LBCM] are set).
As described in Section 22, "Clocking,"
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN
ratios.
CFG_CLKIN_DIV
1
at Reset
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
90
the LBCM, DDRCM, and SPMF parameters in the reset
Table 72. CSB Frequency Options
csb_clk :
SPMF
Input Clock Ratio
0010 2:1
0011 3:1
0100 4:1
0101 5:1
0110 6:1
0111 7:1
1000 8:1
1001 9:1
1010 10:1
1011 11:1
1100 12:1
1101 13:1
1110 14:1
1111 15:1
0000 16:1
0010 2:1
0011 3:1
0100 4:1
0101 5:1
Input Clock Frequency (MHz)
16.67 25
2
csb_clk Frequency (MHz)
100
125
100 150
116 175
133 200
150 225
166 250
183 275
200 300
216 325
233
250
266
Table 72
2
33.33 66.67
133
100 200
133 266
166 333
200
233
266
300
333
133
100 200
133 266
166 333
Freescale Semiconductor