Freescale Semiconductor MPC8358E Hardware Specificftion page 50

JTAG
Figure 29 provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 30 provides the JTAG clock input timing diagram.
JTAG
External Clock
Figure 31 provides the TRST timing diagram.
TRST
Figure 32 provides the boundary-scan timing diagram.
JTAG
External Clock
Boundary
Data Inputs
Boundary
Data Outputs
Boundary
Data Outputs
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
50
= 50 Ω
Z
Output
0
Figure 29. AC Test Load for the JTAG Interface
VM VM
t
JTKHKL
t
JTG
VM = Midpoint Voltage (OV DD /2)
Figure 30. JTAG Clock Input Timing Diagram
VM
VM = Midpoint Voltage (OV DD /2)
Figure 31. TRST Timing Diagram
VM
t
JTKLDV
t
JTKLDX
Output Data Valid
VM = Midpoint Voltage (OV DD /2)
Figure 32. Boundary-Scan Timing Diagram
= 50 Ω
R
L
VM
t
JTGR
VM
t
TRST
VM
t
JTDVKH
Input
Data Valid
Output Data Valid
t
JTKLDZ
OV /2
DD
t
JTGF
t
JTDXKH
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