Pmbus; Psu Address Lines A0; Figure 16. Power Supply Device Address; Table 35. Psu Addressing - Intel H2000WP Technical Manual

Power Sub-System
the power supply temperature drops to within specified limits, the power supply should restore
power automatically, while the 12VSB remains always on. The OTP circuit must have built in
margin, such that the power supply will not oscillate on and off due to temperature recovering
condition. The OTP trip level must have a minimum of 4°C of ambient temperature margin.
3.7

PMBus*

The PMBus* features are requirements for power supply unit for use in server systems. This
specification is based on the PMBus* Specifications part I and II, revision 1.1. The power supply
device address locations are shown below:
The PMBus* from PDB is connected to BMC of all four nodes. Only one board BMC is assigned
to be the master BMC and communicate with PSU as single point. Other board BMCs get the
PSU data from the master BMC. In case the master BMC is down, one of the slave board BMC
will be promoted automatically as the master BMC and maintain the communication.
3.7.1

PSU Address Lines A0

Address pins A0 is used by end use system to allocate unit address to a power supply in
particular slot position.
For redundant systems, there are two signals to set the address location of the power supply
once it is installed in the system; Address0 and Address1. For non-redundant systems, the
power supply device address locations should align with the Address0 / Address1 location of 0/0.
PDB addressing Address0
Power supply PMBus* device
34
Intel

Figure 16. Power Supply Device Address

Table 35. PSU addressing

Intel order number: G52418-006
®
Server System H2000WP Family TPS
0 1
B0h B2h
Revision 1.6