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1.0 Signal/Pin Connection and Description
Component
Resistor R2
Capacitor C1
Capacitor C2
External Elements
Choose C1 and C2 capacitors (see Figure 1) to match the crystal's load capacitance. The load capacitance C
the crystal is comprised of C1 in series with C2, and in parallel with the parasitic capacitance of the circuit. The parasitic
capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 8 pF. The rule of thumb
in choosing these capacitors is:
C
= (C1*C2)/(C1+C2)+C Parasitic
L
1.2.3
USB Port
I/O
Name
I/O
D+
USB D+ Upstream Port. This pin requires an external 1.5k pull-up to 3.3V to signal full speed
operation.
I/O
D–
USB D– Upstream Port
1.2.4
Microprocessor Interface
I/O
Name
I
MODE1-0 Interface Mode. Each of these pins should be hard-wired to V
I
DACK
O
DRQ
O
INTR
I
CS
I
RD
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Parameters
XTAL
C1
C2
Figure 1. Typical Oscillator Circuit
face mode:
MODE1-0 = 00. Mode 0: Non-multiplexed parallel interface mode
MODE1-0 = 01. Mode 1: Multiplexed parallel interface mode
MODE1-0 = 10. Mode 2: MICROWIRE interface mode
MODE1-0 = 11. Mode 3: Reserved
Note: Mode 3 also selects the MICROWIRE interface mode in the USBN9602, but this mode
should be reserved to preserve compatibility with future devices.
DMA Acknowledge. This active low signal is only used if DMA is enabled. If DMA is not used,
this pin must be tied to V
CC
DMA Request. This pin is used for DMA request only if DMA is enabled.
Interrupt. The interrupt signal modes (active high, active low or open drain) can be config-
ured via the Main Control register. During reset, this signal is TRI-STATE
Chip Select. Active low chip select
Read. Active low read strobe, parallel interface
(Continued)
Values
15 pF
15 pF
XIN
R1
XOUT
R2
Description
Description
.
8
Tolerance
ΝΑ
0
±20%
±20%
or GND to select the inter-
CC
.
"seen" by
L
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