Table of Contents
Advertisement
4.0 Direct Memory Access (DMA) Support
The device supports DMA transfers with an external DMA controller from/to endpoints 1 to 6. This mode uses the device
pins DRQ and DACK in addition to the parallel interface pins RD or WR and D7-0 data pins. DMA mode can only be used
with parallel interface mode (MODE1 must be grounded). The read or write address is generated internally and the state of
the A0/ALE pin is ignored during a DMA cycle.
The DMA support logic has a lower priority than the parallel interface. CS must stay inactive during a DMA cycle. If CS be-
comes active, DACK is ignored and a regular read/write operation is performed. Only one endpoint can be enabled at any
given time to issue a DMA request when data is received or transmitted.
Two different DMA modes are supported: standard and automatic.
4.1 STANDARD DMA MODE (DMA)
To enable DMA transfers in standard DMA mode, the following steps must be performed:
1. The local CPU programs the DMA controller for fly-by demand mode transfers. In this mode, transfers occur only when
the device requests them via the DRQ pin. The data is read/written from/to the device receive/transmit FIFO and writ-
ten/read into/from local memory during the same bus transaction.
2. The DMA address counter is programmed to point to the destination memory block in the local shared memory, and the
Byte Count register is programmed with the number of bytes in the block to be transferred. If required the automatic error
handling should be enabled at this point along with the error handling counter. In addition the user needs to set the re-
spective Endpoint enable bit.
3. The DMA Enable bit and DMA Source bits are set in the DMACNTRL register.
4. The USB host can now perform USB bulk or isochronous data transfers over the USB bus to the receive FIFO or from
the transmit FIFO in the device.
5. If the FIFOs warning limit is reached or the transmission/reception is completed, a DMA request/acknowledge sequence
is initiated for the predetermined number of bytes. The time at which a DMA request is issued depends on the selected
DMA mode (controlled by the DMOD bit in the DMACNTRL register), the current status of the endpoint FIFO, and the
FIFO warning enable bits. A DMA request can be issued immediately.
6. After the DMA controller has granted control of the bus, it drives a valid memory address and asserts DACK and RD or
WR, thus transferring a byte from the receive FIFO to memory, or from memory to the transmit FIFO. This process con-
tinues until the DMA byte count, within the DMA controller, reaches zero.
7. After the programmed amount of data is transferred, the firmware must do one of the following (depending on the transfer
direction and mode):
— Queue the new data for transmission by setting the TX_EN bit in the TXCx register.
— Set the End Of Packet marker by setting the TX_LAST bit in the TXCx register. Re-enable reception by setting the
RX_EN bit in the RXCx register.
— Check if the last byte of the packet was received (RX_LAST bit in the RXSx register).
The DMA transfer can be halted at any time by resetting the DMA Request Enable bit. If the DMA Request Enable bit is
cleared during the middle of a DMA cycle, the current cycle is completed before the DMA request is terminated.
See Figures 8 and 9 for the transmit and receive sequences using standard DMA mode.
MIcrocontroller
Set up DMA
Microcontroller
Set up DMA
www.national.com
DMA
Microcontroller
Fill FIFO
Enable TX
Figure 8. Transmit Operation in Standard DMA Mode
Microcontroller
USB
Transaction
Enable RX
Figure 9. Receive Operation in Standard DMA Mode
16
USB
DMA
Fill FIFO
Transaction
Microcontroller
DMA
Enable RX
Read FIFO
time
time
Advertisement
Table of Contents
