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- May 1998
USBN9603/USBN9604 Universal Serial Bus
Full Speed Node Controller with Enhanced DMA Support
General Description
The USBN9603/4 are integrated, USB Node controllers.
Other than the reset mechanism for the clock generation cir-
cuit, these two devices are identical. All references to "the
device" in this document refer to both devices, unless other-
wise noted.
The device provides enhanced DMA support with many au-
tomatic data handling features. It is compatible with USB
specification versions 1.0 and 1.1, and is an advanced ver-
sion of the USBN9602.
The device integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB end-
point (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUS™ interface. Seven
endpoint pipes are supported: one for the mandatory con-
trol endpoint and six to support interrupt, bulk and isochro-
nous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A pro-
grammable interrupt output scheme allows device configu-
ration for different interrupt signaling requirements.
Block Diagram
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© National Semiconductor Corporation, 2003
A0/ALE D7-0/AD7-0
CS
RD
WR
Microcontroller Interface
Endpoint/Control FIFOs
Serial Interface Engine (SIE)
Media Access Controller (MAC)
Physical Layer Interface (PHY)
Transceiver
Upstream Port
D+
D-
Outstanding Features
Low EMI, low standby current, 24 MHz oscillator
Advanced DMA mechanism
Fully static HALT mode with asynchronous wake-up
for bus powered operation
5V or 3.3V operation
Improved input range 3.3V signal voltage regulator
All unidirectional FIFOs are 64 bytes
Power-up reset and startup delay counter simplify sys-
tem design
Simple programming model controlled by external controller
Available in two packages
— USBN9603/4SLB: small footprint for new designs
and portable applications
— USBN9603/4-28M: standard package, pin-to-pin
compatible with USBN9602-28M
INTR
MODE1-0
24 MHz
Oscillator
Clock
Generator
Clock
Recovery
USB Event
Detect
VReg
June 2003
Revision 1.3
RESET
V
CC
GND
XIN
XOUT
CLKOUT
V3.3
AGND
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Table of Contents
Summary of Contents for NS USBN9603
- Page 1 Full Speed Node Controller with Enhanced DMA Support General Description Outstanding Features The USBN9603/4 are integrated, USB Node controllers. Low EMI, low standby current, 24 MHz oscillator Other than the reset mechanism for the clock generation cir- Advanced DMA mechanism cuit, these two devices are identical.
- Page 2 Features Full-speed USB node device Integrated USB transceiver Supports 24 MHz oscillator circuit with internal 48 MHz clock generation circuit Programmable clock generator Serial Interface Engine (SIE) consisting of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Specification 1.0 and 1.1 compliant Control/Status register file USB Function Controller with seven FIFO-based End- points:...
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Page 3: Table Of Contents
Table of Contents Signal/Pin Connection and Description CONNECTION DIAGRAMS ......................6 DETAILED SIGNAL/PIN DESCRIPTIONS .................. 7 1.2.1 Power Supply ........................ 7 1.2.2 Oscillator, Clock and Reset ................... 7 1.2.3 USB Port ........................8 1.2.4 Microprocessor Interface ....................8 Functional Overview TRANSCEIVER ......................... - Page 4 Table of Contents (Continued) 7.1.2 Clock Configuration Register (CCONF)..............31 7.1.3 Revision Identifier (RID) ....................31 7.1.4 Node Functional State Register (NFSR) ..............32 7.1.5 Main Event Register (MAEV) ..................32 7.1.6 Main Mask Register (MAMSK) ..................33 7.1.7 Alternate Event Register (ALTEV)................33 7.1.8 Alternate Mask Register (ALTMSK) ................
- Page 5 Table of Contents (Continued) REGISTER MAP ........................50 Device Characteristics ABSOLUTE MAXIMUM RATINGS .................... 52 DC ELECTRICAL CHARACTERISTICS ................... 52 AC ELECTRICAL CHARACTERISTICS ..................53 PARALLEL INTERFACE TIMING (MODE1-0 = 00B) ..............54 PARALLEL INTERFACE TIMING (MODE1-0 = 01B) ..............55 DMA SUPPORT TIMING ......................
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Page 6: Signal/Pin Connection And Description
1.0 Signal/Pin Connection and Description 1.1 CONNECTION DIAGRAMS 28 27 26 25 24 23 22 WR/SK 28-Pin CSP CLKOUT XOUT RESET AGND MODEO 10 11 12 13 14 USBN9603/4SLB CLKOUT XOUT WR/SK MODE0 INTR MODE1 DACK 28-Pin SO A0/ALE/SI D0/SO D–... -
Page 7: Detailed Signal/Pin Descriptions
1.0 Signal/Pin Connection and Description (Continued) 1.2 DETAILED SIGNAL/PIN DESCRIPTIONS 1.2.1 Power Supply Name Description Digital Power Supply (V ). Power-on reset is detected when the input voltage is at the same level as GND and then raised to the required V level. -
Page 8: Usb Port
1.0 Signal/Pin Connection and Description (Continued) Component Parameters Values Tolerance ΝΑ Resistor R2 ±20% 15 pF Capacitor C1 ±20% 15 pF Capacitor C2 External Elements Choose C1 and C2 capacitors (see Figure 1) to match the crystal’s load capacitance. The load capacitance C “seen”... - Page 9 1.0 Signal/Pin Connection and Description (Continued) Write. Active low write strobe, parallel interface MICROWIRE Shift Clock. Mode 2 A0 Address Bus Line. Mode 0, parallel interface Address Latch Enable. Mode 1, parallel interface MICROWIRE Serial Input. Mode 2 Data Bus Line D0. Mode 0 Address/Data Bus LIne AD0.
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Page 10: Functional Overview
The SIE is also responsible for detecting and reporting USB-specific events, such as NodeReset, NodeSuspend and NodeResume. The module output signals to the transceiver are well matched (under 1 nS) to minimize skew on the USB signals. - Page 11 (Parallel and Serial) A0/ALE/SI Endpoint/Control FIFOs 24 MHz Oscillator XOUT Control Status Clock Generator CLKOUT Clock Media Access Controller (MAC) Recovery USB Event Physical Layer Interface (PHY) Detect V3.3 AGND Transceiver VReg Upstream Port Figure 2. USBN9603/4 Block Diagram www.national.com...
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Page 12: Endpoint Pipe Controller (Epc)
2.0 Functional Overview (Continued) 2.4 ENDPOINT PIPE CONTROLLER (EPC) The EPC provides the interface for USB function endpoints. An endpoint is the ultimate source or sink of data. An endpoint pipe facilitates the movement of data between USB and memory, and completes the path between the USB host and the function endpoint. -
Page 13: Parallel Interface
3.0 Parallel Interface The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its ad- dressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1. 3.1 NON-MULTIPLEXED MODE Non-multiplexed mode uses the control pins CS, RD, WR, the address pin A0 and the bidirectional data bus D7-0 as shown in Figure 4. -
Page 14: Standard Access Mode
3.0 Parallel Interface (Continued) 3.1.1 Standard Access Mode The standard access sequence for non-multiplexed mode is to write the address to the ADDR register and then read or write the data from/to the DATA_OUT/DATA_IN register. The DATA_OUT register is updated after writing to the ADDR register. The ADDR register or the DATA_OUT/DATA_IN register is selected with the A0 input. -
Page 15: Multiplexed Mode
3.0 Parallel Interface (Continued) 3.2 MULTIPLEXED MODE Multiplexed mode uses the control pins CS, RD, WR, the address latch enable signal ALE and the bidirectional address data bus AD7-0 as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to V . -
Page 16: Direct Memory Access (Dma) Support
4.0 Direct Memory Access (DMA) Support The device supports DMA transfers with an external DMA controller from/to endpoints 1 to 6. This mode uses the device pins DRQ and DACK in addition to the parallel interface pins RD or WR and D7-0 data pins. DMA mode can only be used with parallel interface mode (MODE1 must be grounded). -
Page 17: Automatic Dma Mode (Adma)
4.0 Direct Memory Access (DMA) Support (Continued) 4.2 AUTOMATIC DMA MODE (ADMA) The ADMA mode allows the CPU to transfer independently large bulk or isochronous data streams to or from the USB bus. The application’s DMA controller, together with the ADMA logic, have the capability to split a large amount of data and trans- fer it in (FIFO size) packets via the USB. - Page 18 4.0 Direct Memory Access (DMA) Support (Continued) DACK D7-0 Input Figure 12. DMA Write to USBN9603/4 DACK D7-0 Output Figure 13. DMA Read from USBN9603/4 www.national.com...
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Page 19: Microwire/Plus Interface
5.0 MICROWIRE/PLUS Interface The MICROWIRE/PLUS interface allows the device to function as a CPU or microcontroller peripheral via a serial interface. This mode is selected by pulling the MODE1 pin high and the MODE0 pin low. The MICROWIRE/PLUS mode uses the chip select (CS), serial clock (SK), serial data in (SI) and serial data out (SO) pins, as shown in Figure 14. -
Page 20: Read And Write Timing
5.0 MICROWIRE/PLUS Interface (Continued) 5.2 READ AND WRITE TIMING Data is read by shifting in the 2-bit command (CMD and the 6-bit address, RADDR or WADDR) while simultaneously shifting out read data from the previous address. Data can be written in standard or burst mode. Standard mode requires two bytes: one byte for the command and address to be shifted in, and one byte for data to be shifted in. - Page 21 5.0 MICROWIRE/PLUS Interface (Continued) 8 Cycles 8 Cycles 8 Cycles CMD=11 ADDR Write Data Write Data Undefined Data Read Data Read Data Figure 17. Burst Write Timing www.national.com...
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Page 22: Functional Description
6.0 Functional Description 6.1 FUNCTIONAL STATES 6.1.1 Line Condition Detection At any given time, the device is in one of the following states (see Section 6.1.2 for the functional state transitions): • NodeOperational Normal operation • NodeSuspend Device operation suspended due to USB inactivity •... - Page 23 6.0 Functional Description (Continued) set_oper NodeOperational hw/sw reset suspend_det & set_suspend reset_det & set_reset NodeReset resume_compl & set_oper resume_det & set_oper NodeResume NodeSuspend local_event & sd5_detect & clear_suspend reset_det &set_reset Bold Italics = Transition initiated by firmware Notes: 1. When the node is not in NodeOperational state, all registers are frozen with the exception of the endpoint con- troller state machines, and the TX_EN, LAST and RX_EN bits which are reset.
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Page 24: Endpoint Operation
6.0 Functional Description (Continued) 6.2 ENDPOINT OPERATION 6.2.1 Address Detection Packets are broadcast from the host controller to all the nodes on the USB network. Address detection is implemented in hardware to allow selective reception of packets and to permit optimal use of microcontroller bandwidth. One function ad- dress with seven different endpoint combinations is decoded in parallel. - Page 25 6.0 Functional Description (Continued) Table 4. USBN9603/4 Endpoint FIFO Sizes TX FIFO RX FIFO Endpoint No. Size (Bytes) Name Size (Bytes) Name 8 FIFO0 TXFIFO1 RXFIFO1 TXFIFO2 RXFIFO2 TXFIFO3 RXFIFO3 If two endpoints in the same direction are programmed with the same endpoint number and both are enabled, data is re- ceived or transmitted to/from the endpoint with the lower number, until that endpoint is disabled for bulk or interrupt transfers, or becomes full or empty for ISO transfers.
- Page 26 6.0 Functional Description (Continued) A packet written to the FIFO is transmitted if an IN token for the respective endpoint is received. If an error condition is de- tected, the packet data remains in the FIFO and transmission is retried with the next IN token. The FIFO contents can be flushed to allow response to an OUT token or to write new data into the FIFO for the next IN token.
- Page 27 6.0 Functional Description (Continued) TCOUNT Transmit FIFO Count. This value indicates how many empty bytes can be filled within the transmit FIFO. This value is ac- cessible by firmware via the TxSx register. Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) The Receive FIFOs for the Endpoints 2, 4 and 6 support bulk, interrupt and isochronous USB packet transfers larger than the actual FIFO size.
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Page 28: Programming Model
6.0 Functional Description (Continued) 6.2.3 Programming Model Figure 23 illustrates the register hierarchy for event reporting. MAEV RXEV TXEV FWEV ALTEV NAKEV TXS0 TXC0 TXD0 EPC0 RXS0 FIFO0 RXC0 8 byte RXD0 TXSx EPCx TXCx TFIFOx 64 byte TXDx RXSy EPCy RXCx RFIFOy... -
Page 29: Clock Generation
CCONF, and thus no effect on the CLKOUT signal. The only difference between the USBN9603 and USBN9604 devices is the effect of a hardware reset on the clock gener- ation circuit. In the USBN9604, assertion of the RESET input causes the clock generation circuit to be reset, whereas in the USBN9603, the clock generation circuit is not reset. -
Page 30: Register Set
7.0 Register Set The device has a set of memory-mapped registers that can be read from/written to control the USB interface. Some register bits are reserved; reading from these bits returns undefined data. Reserved register bits should always be written with 0. The following conventions are used to describe the register format: Bit Number bit 7... -
Page 31: Clock Configuration Register (Cconf)
7.0 Register Set (Continued) Table 5. Interrupt Output Control Bits INTOC Interrupt Output Disabled Active low open drain Active high push-pull Active low push-pull 7.1.2 Clock Configuration Register (CCONF) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CODIS... -
Page 32: Node Functional State Register (Nfsr)
7.0 Register Set (Continued) 7.1.4 Node Functional State Register (NFSR) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved NFS1-0 Node Functional State. The firmware should initiate all required state transitions according to the respective status bits in the Alternate Event (ALTEV) register. -
Page 33: Main Mask Register (Mamsk)
7.0 Register Set (Continued) TX_EV Transmit Event. This bit is set if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOx or TXUNDRNx) is set. Therefore, it indicates that an IN transaction has been completed. This bit is cleared when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSx) register are cleared. -
Page 34: Alternate Mask Register (Altmsk)
7.0 Register Set (Continued) End of Packet. A valid EOP sequence was detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read. -
Page 35: Transmit Mask Register (Txmsk)
7.0 Register Set (Continued) 7.1.10 Transmit Mask Register (TXMSK) When set and the corresponding bit in the TXEV register is set, TX_EV in the MAEV register is set. When cleared, the cor- responding bit in the TXEV register does not cause TX_EV to be set. bit 7 bit 6 bit 5... -
Page 36: Nak Event Register (Nakev)
7.0 Register Set (Continued) 7.1.13 NAK Event Register (NAKEV) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RXFIFO3 RXFIFO2 RXFIFO1 FIFO0 TXFIFO3 TXFIFO2 TXFIFO1 FIFO0 OUT3-0 IN3-0 Set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Ad- dress, FAR, register is set to 1 and EP_EN in the Endpoint Control, EPCx, register is set to 1) in response to an IN token. -
Page 37: Fifo Warning Mask Register (Fwmsk)
7.0 Register Set (Continued) 7.2.2 FIFO Warning Mask Register (FWMSK) When set and the corresponding bit in the FWEV register is set, WARN in the MAEV register is set. When cleared, the cor- responding bit in the FWEV register does not cause WARN to be set. bit 7 bit 6 bit 5... -
Page 38: Function Address Register (Far)
7.0 Register Set (Continued) 7.2.5 Function Address Register (FAR) This register sets the device function address. The different endpoint numbers are set for each endpoint individually via the Endpoint Control registers. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0... -
Page 39: Dma Event Register (Dmaev)
7.0 Register Set (Continued) A DMA request from a transmit endpoint is activated until the request condition clears. If DMOD is set to 0, DMA requests are issued either until the firmware reads the respective Transmit Status (TXSx) register, thus resetting the TX_DONE bit, or if the TX_LAST bit in the Transmit Command (TXCx) register is set by firmware. -
Page 40: Dma Mask Register (Dmamsk)
7.0 Register Set (Continued) • If the ADMA bit is cleared (but DEN remains set). In this case, the current operation (if any) is completed. This means that any data in the FIFO is either transmitted or transferred to memory by DMA (if receiving). The DSHLT bit is set only after this has occurred. -
Page 41: Mirror Register (Mir)
7.0 Register Set (Continued) 7.2.9 Mirror Register (MIR) This is a read only register. Since reading it does not alter the state of the TXSx or RXSx register to which it points, the firmware can freely check the status of the channel. bit 7 bit 6 bit 5... -
Page 42: Wake-Up Register (Wkup)
7.0 Register Set (Continued) Automatic Error Handling. This bit has two different meanings, depending on the current transaction mode: Non-Isochronous mode This mode is used for bulk, interrupt and control transfers. Setting AEH in this mode enables automatic handling of packets containing CRC or bit-stuffing errors. -
Page 43: Endpoint Control 0 Register (Epc0)
7.0 Register Set (Continued) 7.2.13 Endpoint Control 0 Register (EPC0) This register controls mandatory Endpoint Control 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STALL Reserved EP3-0 r; hardwired to 0 Endpoint. -
Page 44: Transmit Command 0 Register (Txc0)
7.0 Register Set (Continued) 7.2.15 Transmit Command 0 Register (TXC0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved IGN_IN FLUSH TOGGLE Reserved TX_EN r/w HW r/w HW TX_EN Transmission Enable. This bit enables data transmission from the FIFO. It is cleared by the chip after transmitting a single packet, or a STALL handshake, in response to an IN token. -
Page 45: Receive Command 0 Register (Rxc0)
7.0 Register Set (Continued) RX_LAST Receive Last Bytes. Indicates that an ACK was sent upon completion of a successful receive operation. This bit is un- changed for zero length packets. It is cleared when this register is read. TOGGLE This bit specified the PID used when receiving the packet. A value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. -
Page 46: Endpoint Control X Register (Epc1 To Epc6)
7.0 Register Set (Continued) 7.2.20 Endpoint Control X Register (EPC1 to EPC6) Each unidirectional endpoint has an EPCx register with the bits defined below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STALL Reserved EP_EN... -
Page 47: Transmit Command X Register (Txc1, Txc2, Txc3)
7.0 Register Set (Continued) For ISO operation, this bit is set if a frame number LSB match (see “IGN_ISOMSK” bit in Section 7.2.22) occurs, and data was sent in response to an IN token. Otherwise, this bit is reset, the FIFO is flushed and TX_DONE is set. This bit is also cleared when this register is read. -
Page 48: Transmit Data X Register (Txd1, Txd2, Txd3)
7.0 Register Set (Continued) Table 8. Set Transmit FIFO Warning Limit TFWL Bytes Remaining in FIFO TFWL disabled ≤ 4 ≤ 8 ≤ 16 IGN_ISOMSK Ignore ISO Mask. This bit has an effect only if the endpoint is set to be isochronous. If set, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. -
Page 49: Receive Command X Register (Rxc1, Rxc2, Rxc3)
7.0 Register Set (Continued) For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset to 0 by reading the RXSx register. SETUP This bit indicates that the setup packet has been received. It is cleared when this register is read. RX_ERR Receive Error. -
Page 50: Receive Data X Register (Rxd1, Rxd2, Rxd3)
The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine. 7.3 REGISTER MAP Table 10 lists all device registers, their addresses and their abbreviations. Table 10. USBN9603/4 Memory Map Register Address Register Name... - Page 51 7.0 Register Set (Continued) Register Address Register Name Mnemonic 0x18 DMACNT DMA Count 0x19 DMAERR DMA Error Count 0x1A Reserved 0x1B WKUP Wake-Up 0x1C - 0x1F Reserved 0x20 EPC0 Endpoint Control 0 0x21 TXD0 Transmit Data 0 0x22 TXS0 Transmit Status 0 0x23 TXC0 Transmit Command 0...
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Page 52: Device Characteristics
8.0 Device Characteristics 8.1 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limits beyond which damage to the device may occur. Supply Voltage -0.5V to +7.0V -0.5V to V +0.5V DC Input Voltage -0.5V to V +0.5V DC Output Voltage Storage Temperature -65˚C to +150˚C Lead Temperature (Soldering 10 seconds) 260˚C... -
Page 53: Ac Electrical Characteristics
8.0 Device Characteristics (Continued) Symbol Parameter Conditions Units Input Low Voltage µA = GND Input Low Current µA Input High Current µA or GND Tri-state Leakage Oscillator Input/Output Signals (XTALIN, XTALOUT) 4, 5 Input High Switching Level 4, 5 Input Low Switching Level Input Capacitance Output Capacitance XOUT... -
Page 54: Parallel Interface Timing (Mode1-0 = 00B)
8.0 Device Characteristics (Continued) Note: CKI in the following tables refers to the internal clock of the device and not to the signal frequency applied at XIN. 8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00 (3.0V< V < 5.5V, 0˚C < TA< +70˚C, unless otherwise specified) Symbol Parameter Conditions... -
Page 55: Parallel Interface Timing (Mode1-0 = 01B)
8.0 Device Characteristics (Continued) D7-0 Input Valid Valid Figure 26. Non-Multiplexed Mode Write Timing (Consecutive Write Cycles Shown) Note: The setup and hold times t and t are defined relative to the first transition of either CS or WR. Both signals may switch at the same time. 8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01 (3.0V<... - Page 56 8.0 Device Characteristics (Continued) CLAL ALRH RHDZ AVAL RLDV AHAL AD7-0 ADDR DATA Figure 27. Multiplexed Mode Interface Read Timing WHAH CLAL WHCH DSWH DHWH AVAL AHAL AD7-0 ADDR DATA Figure 28. Multiplexed Mode Interface Write Timing www.national.com...
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Page 57: Dma Support Timing
2. If DMA transfer is not interrupted by read or write. If the transfer is interrupted, two additional MCLK cycles are used. RHAL DACK ALWL Input D7-0 Figure 29. DMA Write to USBN9603/4 RHAL DACK ALRL D7-0 Output Figure 30. DMA Read from USBN9603/4... -
Page 58: Microwire Interface Timing (Mode1-0 = 10B)
8.0 Device Characteristics (Continued) 8.7 MICROWIRE INTERFACE TIMING (MODE1-0 = 10 Symbol Parameter Condition Units = 50 pF 8/MCLK SK Cycle Time Time between two consecutive = 50 pF 4/MCLK 8 clock cycles = 50 pF 3/MCLK Serial Input Hold Time = 50 pF 3/MCLK Serial Output Valid Time... - Page 59 Physical Dimensions Inches (millimeters) unless otherwise noted Laminate Substrate Based Package Order Number USBN9603/4SLB See NS Package Number SLB28AA Molded SO Wide Body Package (WM) Order Number USBN9603/4-28M See NS Package Number M28B www.national.com...
- Page 60 PC87360 ADVANCE INFORMATION LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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