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8.0 Device Characteristics
Note: CKI in the following tables refers to the internal clock of the device and not to the signal frequency applied at XIN.
8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00
(3.0V< V
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
CC
Symbol
t
Address Setup Time
AS
t
Address Hold Time
AH
t
Read Pulse Width
RW
t
Read Cycle Time
RC
t
Data Output Valid after Read Low
RDV
t
Data Output Hold after Read High
RDH
t
Write Pulse Width
WW
t
Write Cycle Time
WC
t
Data Input Setup Time
DS
t
Data Input Hold Time
DH
1. Clock Internal: CKI = 48 MHz on this device
2. Memory Clock: MCLK = CKI/4 = 12 MHz
3. Time until next read or write occurs
D7-0 Output
Note: The setup time t
may switch at the same time.
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(Continued)
B
Parameter
1
2 3
1
2 3
CS
A0
t
AS
t
RW
RD
t
RDV
Valid
Figure 25. Non-Multiplexed Mode Read Timing
(Consecutive Read Cycles Shown)
is defined relative to the first transition of either CS or RD. Both signals
AS
)
Conditions
Min
C
= 50 pF
0
L
C
= 50 pF
0
L
C
= 50 pF
1/CKI
L
C
= 50 pF
3/MCLK
L
C
= 50 pF
L
C
= 50 pF
2
L
C
= 50 pF
1/CKI
L
C
= 50 pF
3/MCLK
L
C
= 50 pF
25
L
C
= 50 pF
8
L
t
RC
t
RDH
Valid
54
Typ
Max
Units
nS
nS
nS
nS
20
30
nS
nS
nS
nS
nS
nS
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