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6.0 Functional Description
6.2.3
Programming Model
Figure 23 illustrates the register hierarchy for event reporting.
.
FWEV
6.3 POWER SAVING MODES
To minimize the power consumption of the USB node, the device can be set to a static Halt mode. During Halt mode, the
clock oscillator circuit is disabled, stopping the external 24 MHz clock and 48 MHz frequency doubler, as well as the clock
output signal provided on the CLKOUT pin. However, all device internal status and register settings are preserved.
The device is set to Halt mode under the following conditions:
If Halt On Suspend (HOS) is enabled (the HOS bit in the WKUP register is set to 1), the device enters Halt mode
when the node is set in Suspend state. Writing a 1 to HOS after the node is in Suspend state has no effect.
If the node is not attached, the device enters Halt mode, when the Force Halt bit (FHT) in the Wake-Up register is
set to 1.
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(Continued)
RXEV
TXEV
Figure 23. Register Hierarchy
28
MAEV
ALTEV
TXS0
TXC0
TXD0
RXS0
RXC0
RXD0
TXSx
TXCx
TXDx
RXSy
RXCx
RXDy
NAKEV
EPC0
FIFO0
8 byte
EPCx
TFIFOx
64 byte
EPCy
RFIFOy
64 byte
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