Receive Data X Register (Rxd1, Rxd2, Rxd3); Register Map - NS USBN9603 Manual

7.0 Register Set
(Continued)

7.2.26 Receive Data X Register (RXD1, RXD2, RXD3)

Each of the three Receive Endpoint FIFOs has one Receive Data register with the bits defined below.
bit 7
RXFD
Receive FIFO Data Byte. See "Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)" in Section 6.2.2 for a
description of Endpoint FIFO data handling.
The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state
machine.

7.3 REGISTER MAP

Table 10 lists all device registers, their addresses and their abbreviations.
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bit 6 bit 5 bit 4
Table 10. USBN9603/4 Memory Map
Register
Address
Mnemonic
0x00 MCNTRL
0x01 CCONF
0x02
0x03 RID
0x04 FAR
0x05 NFSR
0x06 MAEV
0x07 MAMSK
0x08 ALTEV
0x09 ALTMSK
0x0A TXEV
0x0B TXMSK
0x0C RXEV
0x0D RXMSK
0x0E NAKEV
0x0F NAKMSK
0x10 FWEV
0x11 FWMSK
0x12 FNH
0x13 FNL
0x14 DMACNTRL
0x15 DMAEV
0x16 DMAMSK
0x17 MIR
bit 3 bit 2
RXFD
-
r
Register Name
Main Control
Clock Configuration
Reserved
Revision Identifier
Function Address
Node Functional State
Main Event
Main Mask
Alternate Event
Alternate Mask
Transmit Event
Transmit Mask
Receive Event
Receive Mask
NAK Event
NAK Mask
FIFO Warning Event
FIFO Warning Mask
Frame Number High Byte
Frame Number Low Byte
DMA Control
DMA Event
DMA Mask
Mirror
50
bit 1 bit 0