Receive Command 0 Register (Rxc0); Receive Data 0 Register (Rxd0) - NS USBN9603 Manual

7.0 Register Set
(Continued)
RX_LAST
Receive Last Bytes. Indicates that an ACK was sent upon completion of a successful receive operation. This bit is un-
changed for zero length packets. It is cleared when this register is read.
TOGGLE
This bit specified the PID used when receiving the packet. A value of 0 indicates that the last successfully received packet
had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. This bit is unchanged for zero length pack-
ets. It is cleared when this register is read.
SETUP
This bit indicates that the setup packet has been received. This bit is unchanged for zero length packets. It is cleared when
this register is read.

7.2.18 Receive Command 0 Register (RXC0)

bit 7 bit 6
Reserved
RX_EN
Receive Enable. OUT packet reception is disabled after every data packet is received, or when a STALL handshake is re-
turned in response to an OUT token. A 1 must be written to this bit to re-enable data reception. Reception of SETUP packets
is always enabled. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet is re-
ceived with no other intervening non-SETUP tokens, the Endpoint Controller discards the new SETUP packet and returns
an ACK handshake. If any other reasons prevent the Endpoint Controller from accepting the SETUP packet, it must not gen-
erate a handshake. This allows recovery from a condition where the ACK of the first SETUP token was lost by the host.
IGN_OUT
Ignore OUT tokens. When this bit is set, the endpoint ignores any OUT tokens directed to its configured address.
IGN_SETUP
Ignore SETUP tokens. When this bit is set, the endpoint ignores any SETUP tokens directed to its configured address.
FLUSH
Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read
and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on USB, flushing is delayed
until after the transfer is done. This bit is cleared on reset. This bit is equivalent to FLUSH in the TXC0 register.

7.2.19 Receive Data 0 Register (RXD0)

bit 7
RXFD
Receive FIFO Data Byte. See "Bidirectional Control Endpoint FIFO0 Operation" in Section 6.2.2 for a description of data
handling.
The firmware should expect to read only the packet payload data. The PID and CRC16 are removed from the incoming data
stream automatically.
bit 5 bit 4 bit 3
FLUSH
- 0
- r/w HW
bit 6 bit 5 bit 4
bit 2
IGN_SETUP IGN_OUT
0
r/w
bit 3 bit 2
RXFD
-
r/w
45
bit 1 bit 0
RX_EN
0 0
r/w r/w
bit 1 bit 0
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