Transmit Mask Register (Txmsk); Receive Event Register (Rxev); Receive Mask Register (Rxmsk) - NS USBN9603 Manual

7.0 Register Set
(Continued)

7.1.10 Transmit Mask Register (TXMSK)

When set and the corresponding bit in the TXEV register is set, TX_EV in the MAEV register is set. When cleared, the cor-
responding bit in the TXEV register does not cause TX_EV to be set.
bit 7
0

7.1.11 Receive Event Register (RXEV)

bit 7
RXFIFO3 RXFIFO2 RXFIFO1
0
RXFIFO
Receive FIFO. These bits are set whenever either RX_ERR or RX_LAST in the respective Receive Status (RXSx) register
is set. Reading the corresponding RXSx register automatically clears these bits.
The device discards all packets for Endpoint 0 received with errors. This is necessary in case of retransmission due to media
errors, ensuring that a good copy of a SETUP packet is captured. Otherwise, the FIFO may potentially be tied up, holding
corrupted data and unable to receive a retransmission of the same packet (the RXFIFO0 bit does only reflect the value of
RX_LAST for Endpoint 0).
If data streaming is used for the receive endpoints (EP2, EP4 and EP6) the firmware must check with the respective
RX_ERR bits to ensure the packets received are not corrupted by errors.
RXOVRRN
Receive Overrun. These bits are set in the event of a FIFO overrun condition. They are cleared when the register is read.
The firmware must check with the respective RX_ERR bits that packets received for the other receive endpoints (EP2, EP4
and EP6) are not corrupted by errors, as these endpoints support data streaming (packets which are longer than the actual
FIFO depth).

7.1.12 Receive Mask Register (RXMSK)

When set and the corresponding bit in the RXEV register is set, RX_EV in the MAEV register is set. When cleared, the cor-
responding bit in the RXEV register does not cause RX_EV to be set.
bit 7
0
bit 6 bit 5 bit 4
Same Bit Definition as TXEV Register
0 0 0
bit 6 bit 5 bit 4
FIFO0
RXOVRRN3-0
0 0 0
CoR
bit 6 bit 5 bit 4
Same Bit Definition as RXEV Register
0 0 0
bit 3 bit 2
0 0
r/w
bit 3 bit 2
RXFIFO3 RXFIFO2 RXFIFO1
RXFIFO3-0
0 0
r
bit 3 bit 2
0 0
r/w
35
bit 1 bit 0
0 0
bit 1 bit 0
FIFO0
0 0
bit 1 bit 0
0 0
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